EPM7128EQC100-10 vs EPM7128AETC100-10N Comparison
Detailed side-by-side comparison of EPM7128EQC100-10 by Altera and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128EQC100-10 | EPM7128AETC100-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $9.95 |
| Family | MAX 7000 | MAX 7000AE |
| Logic Family | CPLD - Complex Programmable Logic Device | β |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| Logic Array Blocks (LABs) | 4 | β |
| User I/O Pins | 84 | β |
| Propagation Delay (tpd) | 10 ns | β |
| Internal Performance | 100 MHz | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Technology | 5.0 V CMOS, EEPROM-based | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | β |
| Package | 100-pin PQFP (Plastic Quad Flat Pack), gull-wing leads | TQFP-100 |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 Β°C to +90 Β°C (Commercial) | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Series | β | EPM7128AE |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | β | 16 |
| User I/Os | β | 84 |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Tolerance | β | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Speed Grade | β | -10 |
| Maximum Frequency | β | [DATA_NEEDED: maximum toggle frequency] |
| Programming | β | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Process Technology | β | CMOS EEPROM |
| Architecture | β | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | β | Yes (33 MHz, -10 grade per PCI SIG 2.2) |