EPM7128EQC100-10 - 128-Macrocell MAX 7000 CPLD, 10ns, PQFP-100
MPN: EPM7128EQC100-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM7128EQC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC100-10
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128AETC100-10
β Drop-Inβ In Stock
$13.85 / Unit
View Datasheet βEPM7128AETC100-10N
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128ATC100-10
β Drop-Inβ In Stock
$4.95 / Unit
View Datasheet βEPM7128ATC100-7F
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128BTC100-10
β Drop-Inβ In Stock
$11.2 / Unit
View Datasheet βEPM7128EQC100-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Logic Family | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 84 |
| Propagation Delay (tpd) | 10 ns |
| Internal Performance | 100 MHz |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| Technology | 5.0 V CMOS, EEPROM-based |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 100-pin PQFP (Plastic Quad Flat Pack), gull-wing leads |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 Β°C to +90 Β°C (Commercial) |
EPM7128EQC100-10 Pin Configuration
| Pin 1 | I/O β User I/O (macrocell pin) |
| Pin 2 | I/O β User I/O (macrocell pin) |
| Pin 3 | I/O β User I/O (macrocell pin) |
| Pin 4 | I/O β User I/O (macrocell pin) |
| Pin 5 | I/O β User I/O (macrocell pin) |
| Pin 6 | I/O β User I/O (macrocell pin) |
| Pin 7 | I/O β User I/O (macrocell pin) |
| Pin 8 | I/O β User I/O (macrocell pin) |
| Pin 9 | I/O β User I/O (macrocell pin) |
| Pin 10 | I/O β User I/O (macrocell pin) |
| Pin 11 | I/O β User I/O (macrocell pin) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O (macrocell pin) |
| Pin 14 | I/O β User I/O (macrocell pin) |
| Pin 15 | I/O β User I/O (macrocell pin) |
| Pin 16 | I/O β User I/O (macrocell pin) |
| Pin 17 | I/O β User I/O (macrocell pin) |
| Pin 18 | I/O β User I/O (macrocell pin) |
| Pin 19 | I/O β User I/O (macrocell pin) |
| Pin 20 | I/O β User I/O (macrocell pin) |
| Pin 21 | I/O β User I/O (macrocell pin) |
| Pin 22 | I/O β User I/O (macrocell pin) |
| Pin 23 | I/O β User I/O (macrocell pin) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O (macrocell pin) |
| Pin 26 | I/O β User I/O (macrocell pin) |
| Pin 27 | I/O β User I/O (macrocell pin) |
| Pin 28 | I/O β User I/O (macrocell pin) |
| Pin 29 | I/O β User I/O (macrocell pin) |
| Pin 30 | I/O β User I/O (macrocell pin) |
| Pin 31 | I/O β User I/O (macrocell pin) |
| Pin 32 | I/O β User I/O (macrocell pin) |
| Pin 33 | I/O β User I/O (macrocell pin) |
| Pin 34 | I/O β User I/O (macrocell pin) |
| Pin 35 | VCC β +5 V supply |
| Pin 36 | I/O β User I/O (macrocell pin) |
| Pin 37 | I/O β User I/O (macrocell pin) |
| Pin 38 | I/O β User I/O (macrocell pin) |
| Pin 39 | I/O β User I/O (macrocell pin) |
| Pin 40 | I/O β User I/O (macrocell pin) |
| Pin 41 | I/O β User I/O (macrocell pin) |
| Pin 42 | I/O β User I/O (macrocell pin) |
| Pin 43 | I/O β User I/O (macrocell pin) |
| Pin 44 | I/O β User I/O (macrocell pin) |
| Pin 45 | I/O β User I/O (macrocell pin) |
| Pin 46 | GND β Ground |
| Pin 47 | I/O β User I/O (macrocell pin) |
| Pin 48 | I/O β User I/O (macrocell pin) |
| Pin 49 | I/O β User I/O (macrocell pin) |
| Pin 50 | I/O β User I/O (macrocell pin) |
| Pin 51 | I/O β User I/O (macrocell pin) |
| Pin 52 | I/O β User I/O (macrocell pin) |
| Pin 53 | I/O β User I/O (macrocell pin) |
| Pin 54 | I/O β User I/O (macrocell pin) |
| Pin 55 | I/O β User I/O (macrocell pin) |
| Pin 56 | I/O β User I/O (macrocell pin) |
| Pin 57 | I/O β User I/O (macrocell pin) |
| Pin 58 | VCC β +5 V supply |
| Pin 59 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 60 | TMS β JTAG Test Mode Select |
| Pin 61 | TCK β JTAG Test Clock |
| Pin 62 | I/O β User I/O (macrocell pin) |
| Pin 63 | I/O β User I/O (macrocell pin) |
| Pin 64 | I/O β User I/O (macrocell pin) |
| Pin 65 | I/O β User I/O (macrocell pin) |
| Pin 66 | I/O β User I/O (macrocell pin) |
| Pin 67 | I/O β User I/O (macrocell pin) |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O (macrocell pin) |
| Pin 70 | I/O β User I/O (macrocell pin) |
| Pin 71 | I/O β User I/O (macrocell pin) |
| Pin 72 | I/O β User I/O (macrocell pin) |
| Pin 73 | I/O β User I/O (macrocell pin) |
| Pin 74 | I/O β User I/O (macrocell pin) |
| Pin 75 | I/O β User I/O (macrocell pin) |
| Pin 76 | I/O β User I/O (macrocell pin) |
| Pin 77 | I/O β User I/O (macrocell pin) |
| Pin 78 | I/O β User I/O (macrocell pin) |
| Pin 79 | I/O β User I/O (macrocell pin) |
| Pin 80 | VCC β +5 V supply |
| Pin 81 | I/O β User I/O (macrocell pin) |
| Pin 82 | I/O β User I/O (macrocell pin) |
| Pin 83 | I/O β User I/O (macrocell pin) |
| Pin 84 | I/O β User I/O (macrocell pin) |
| Pin 85 | I/O β User I/O (macrocell pin) |
| Pin 86 | I/O β User I/O (macrocell pin) |
| Pin 87 | I/O β User I/O (macrocell pin) |
| Pin 88 | I/O β User I/O (macrocell pin) |
| Pin 89 | I/O β User I/O (macrocell pin) |
| Pin 90 | I/O β User I/O (macrocell pin) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O (macrocell pin) |
| Pin 93 | I/O β User I/O (macrocell pin) |
| Pin 94 | I/O β User I/O (macrocell pin) |
| Pin 95 | I/O β User I/O (macrocell pin) |
| Pin 96 | I/O β User I/O (macrocell pin) |
| Pin 97 | I/O β User I/O (macrocell pin) |
| Pin 98 | I/O β User I/O (macrocell pin) |
| Pin 99 | I/O β User I/O (macrocell pin) |
| Pin 100 | TDO β JTAG Test Data Out (IEEE 1149.1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128EQC100-10 is suitable for 6 applications: Microcontroller Bus Interface Bridging, Address Decoding and Chip-Select Generation, Legacy 74-Series TTL Integration, Industrial Control and PLC Logic, Telecommunications Line-Card Glue Logic, Test and Measurement Equipment Front-End.
Microcontroller Bus Interface Bridging
The EPM7128EQC100-10's 84 user I/O pins and 10 ns deterministic tpd make it well suited to bridging between microcontrollers and peripherals with mismatched bus widths or timing. With 128 macrocells across four LABs, it can implement multiple address-latch, chip-select, and wait-state generators in a single chip. The 5 V tolerant I/O directly interfaces with legacy 8051, 68HC11, and similar MCU buses without level shifters, and the deterministic timing allows reliable glue logic replacement of dozens of 74-series TTL packages.
Recommended
Address Decoding and Chip-Select Generation
The EPM7128EQC100-10 is widely used as an address decoder in 8/16/32-bit embedded systems, where it generates chip-selects for memory banks and peripherals from a single address bus. The 128 macrocells easily accommodate full 24-bit address decoding with multiple chip-enable outputs, while the 10 ns propagation delay ensures CS-valid timing is met before memory access windows close. Non-volatile EEPROM configuration means no boot PROM is required, simplifying BOM and reducing board space compared to discrete decoder PALs.
Recommended
Legacy 74-Series TTL Integration
The EPM7128EQC100-10 was historically used to replace entire boards of 74LS/74HC glue logic - latches, multiplexers, decoders, shifters, and state machines - with a single non-volatile device. The MAX 7000 macrocell structure maps directly onto classic AND-OR PLA patterns, easing migration of legacy TTL schematics. With 2,500 usable gates and 84 I/Os, a single EPM7128EQC100-10 typically replaces 10-20 discrete packages, reducing PCB area and improving long-term availability of obsolete TTL parts.
Recommended
Industrial Control and PLC Logic
The EPM7128EQC100-10's commercial 0-90 Β°C operating range, 5 V supply tolerance, and instant-on non-volatile configuration make it suitable for industrial control boards and PLC peripheral modules. The deterministic 10 ns timing supports hard-real-time control loops where predictability outweighs raw speed. Industrial designers value the JTAG ISP path for field firmware updates, and the PQFP-100 package's surface-mount compatibility supports modern SMT assembly lines for medium-volume control products.
Recommended
Telecommunications Line-Card Glue Logic
In telecom line cards and access equipment, the EPM7128EQC100-10 provides deterministic timing for E1/T1 framers, HDLC controllers, and time-slot interchangers. The 128 macrocells handle multiple independent functions - alarm generation, loop-back control, and LED status multiplexing - with the 10 ns delay fitting comfortably within standard telecom timing budgets. The 5 V tolerant I/Os interface directly with legacy telecom ASICs, and the non-volatile configuration eliminates boot-time variability critical for carrier-grade equipment.
Recommended
Test and Measurement Equipment Front-End
Test instruments such as logic analyzers, protocol testers, and bench-top emulators use the EPM7128EQC100-10 for pattern generation, channel multiplexing, and trigger sequencing. The 100 MHz internal performance supports fast pattern rates while the deterministic tpd simplifies timing analysis in test setups. With 84 I/Os available, multiple test channels can be routed through a single device, and the JTAG interface enables easy firmware updates as test protocols evolve during product development.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128EQC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC100-10 | EPM7128AETC100-10 | EPM7128AETC100-10N | EPM7128ATC100-10 | EPM7128ATC100-7F | EPM7128BTC100-10 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-100 | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tpd) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 7 ns (-30%, faster) | 10 ns |
| Family | MAX 7000 (non-S) | MAX 7000S (ISP-capable) | MAX 7000A | MAX 7000A (lead-free) | MAX 7000A | MAX 7000A (faster speed) | MAX 7000B |
| User I/O Pins | 84 | 84 | 84 | 84 | 84 | 84 | 84 |
| Internal Performance | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 125 MHz (+25%) | 100 MHz |
| Supply Voltage | 4.75 V to 5.25 V (5 V) | 4.75 V to 5.25 V | 3.0 V to 3.6 V or 5 V variant | 3.0 V to 3.6 V or 5 V variant | 3.0 V to 3.6 V or 5 V variant | 3.0 V to 3.6 V or 5 V variant | 2.5 V or 3.3 V (lower) |
| RoHS / Lead-Free | [DATA_NEEDED] | Often non-RoHS (legacy) | Often non-RoHS (legacy) | Pb-free variant (RoHS-friendly) | Often non-RoHS (legacy) | Often non-RoHS (legacy) | Often non-RoHS (legacy) |
Key Differentiators
- Non-volatile EEPROM configuration - no boot PROM required (vs EPM7128SQC100-10)
- 5 V native operation with 84 user I/Os (vs XCR3064XL-10VQG44)
- Industry-standard PQFP-100 footprint with broad second-source support (vs EPM7128ATC100-10)
Design Notes
Estimated: The EPM7128EQC100-10 typically draws ~50-150 mA quiescent current at 5 V depending on output switching activity. Provide at least one 0.1 Β΅F ceramic decoupling capacitor adjacent to each VCC/GND pair (the PQFP-100 has 3 VCC and 3 GND pins spread around the package) plus a single bulk 10 Β΅F tantalum or low-ESR electrolytic cap on the supply rail. Estimated input values used: VCC = 5.0 V, ICC = 100 mA typical, decoupling per MAX 7000 datasheet recommendations.
PQFP-100 packages require careful thermal and signal-integrity layout. Use a 4-layer PCB with a dedicated ground plane under the device to provide the low-impedance return path for the high-edge-rate I/O drivers. Route JTAG signals (TCK, TMS, TDI, TDO) as a short chain with series damping near the connector; the JTAG chain is sensitive to reflections and ground bounce. Keep clock inputs away from high-slew-rate outputs to avoid coupling into LAB sense amplifiers.
Estimated: When programming in-system via JTAG, ensure VCC is stable and within 4.75-5.25 V before asserting TCK - programming below this threshold can corrupt the EEPROM configuration. Always issue a JTAG bulk-erase before re-programming a part from an unknown source, and verify the IDCODE via Quartus before write operations. Estimated input: standard JTAG programming voltage 5.0 V, threshold per MAX 7000 datasheet ISP specification. Note that this part is obsolete - validate the JTAG chain with a known-good device before relying on it for production programming.
The EPM7128EQC100-10 in PQFP-100 has a typical theta-JA of around 50 Β°C/W (per MAX 7000 family datasheet). For commercial 0-90 Β°C operation at moderate switching activity, no heatsink is required. For sustained high-activity designs (e.g., continuously clocked counters), verify junction temperature using the EPM7128 power calculator - the I/O drive strength contributes significant dynamic power that scales with toggle rate.
Compliance Information
RoHS/REACH/lead-free status not explicitly listed in verified distributor data for this obsolete part. Original MAX 7000 family parts from this era are typically non-RoHS - the 'N' suffix variants (e.g. EPM7128AETC100-10N) are the lead-free / RoHS-friendly alternatives from the same family.
