EPM7128SLC84-15 vs EPM7128ELC84-12 Comparison
Detailed side-by-side comparison of EPM7128SLC84-15 by Intel and EPM7128ELC84-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 β Last Time BuySpecification Comparison
| Parameter | EPM7128SLC84-15 | EPM7128ELC84-12 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $10.40 |
| Family | MAX 7000S | MAX 7000 (MAX 7000E series) |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 68 (in 84-PLCC) | 84 |
| Package | 84-Pin PLCC (J-Lead, J84) | 84-pin PLCC (J-Lead, QCCJ) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | β |
| Propagation Delay (tPD) | 15 ns | β |
| Maximum Internal Frequency (fMAX) | 76.9 MHz | β |
| Logic Family / Process | CMOS, 5V, EEPROM | β |
| Supply Voltage (VCCINT) | 5 V | β |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) | β |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | JTAG (IEEE 1149.1) / ISP |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Non-RoHS (legacy 5V part) | Non-compliant (legacy 5V part, SnPb finish) |
| Mounting Type | Surface Mount / Socketed (PLCC-84 socket) | Surface Mount (PLCC socket compatible) |
| Logic Family | β | CMOS, EEPROM-based |
| Logic Array Blocks (LABs) | β | 8 |
| Propagation Delay (tpd1) | β | 12 ns |
| Internal Global Clock Frequency | β | 90.9 MHz |
| Setup Time | β | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | β | 5 V (4.75 V to 5.25 V) |
| Pin Count | β | 84 |