EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
MPN: EPM7128SLC84-15 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.4 | $10,400.00 |
Drop-in alternatives for EPM7128SLC84-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128SLC84-10
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPM7128SLC84-15N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128ELC84-20
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$24.2 / Unit
View Datasheet →EPM7128ELC84-12
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$10.4 / Unit
View Datasheet →EPM7128ELC84-10
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$7.2 / Unit
View Datasheet →EPM7128AELC84-10N
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$10.45 / Unit
View Datasheet →EPM7096LC84-15
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPM7128SLC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 68 (in 84-PLCC) |
| Package | 84-Pin PLCC (J-Lead, J84) |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Frequency (fMAX) | 76.9 MHz |
| Logic Family / Process | CMOS, 5V, EEPROM |
| Supply Voltage (VCCINT) | 5 V |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Non-RoHS (legacy 5V part) |
| Mounting Type | Surface Mount / Socketed (PLCC-84 socket) |
EPM7128SLC84-15 Pin Configuration
| Pin 1 | TDI — JTAG Test Data In |
| Pin 2 | I/O — User I/O pin (LAB signal) |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | VCCINT — 5V core supply |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | GND — Ground |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | TCK — JTAG Test Clock |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | VCCIO — I/O supply voltage (5V) |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | TMS — JTAG Test Mode Select |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | VCCINT — 5V core supply |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | GND — Ground |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | TDO — JTAG Test Data Out |
| Pin 84 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SLC84-15 is suitable for 6 applications: Industrial PLC Glue Logic, Legacy x86 Embedded Bus Decoding, Telecommunications Backplane Bridging, ASIC Prototype Logic Replacement, Medical Device Interface Logic, Test & Measurement Instrument Front End.
Industrial PLC Glue Logic
The EPM7128SLC84-15 fits industrial PLC glue-logic applications because its 128 macrocells provide ample capacity to implement address decoding, bus arbitration, and custom state machines between the CPU, I/O modules, and communication ASICs, while its 5V-tolerant I/O bank eliminates level-shifters when bridging legacy TTL peripherals. The 15 ns pin-to-pin propagation delay (76.9 MHz fMAX) supports deterministic timing for scan-path control and deterministic interrupt handling in ladder-logic translation. Instant-on EEPROM configuration is critical for PLC boot sequences where SRAM-based FPGAs would require a separate boot PROM and add milliseconds to startup. Compared with a discrete 74HC logic implementation, a single EPM7128SLC84-15 replaces dozens of packages and reduces PCB area by 60-80 percent.
Recommended
Legacy x86 Embedded Bus Decoding
The EPM7128SLC84-15 is ideal for legacy x86 embedded bus-decoding applications such as ISA-bus chip-select generation, wait-state insertion, and DRAM address multiplexing, where the 128 macrocells can implement wide combinational decoder logic in a single device. Its 5V VCCINT and 5V-tolerant I/O directly interface with ISA-bus signal levels without level shifters, and the 15 ns tPD provides the timing margin needed for 8 MHz and 16 MHz ISA cycles. The 84-PLCC socket-friendly package simplifies field replacement and legacy board bring-up. Compared with PAL/GAL decoding trees, the MAX 7000S reduces chip count by 5-10x and adds JTAG-reprogrammability that speeds up address-map revisions.
Recommended
Telecommunications Backplane Bridging
The EPM7128SLC84-15 fits telecommunications backplane-bridging roles by providing deterministic glue logic between line cards, framer ASICs, and TDM bus switches, where the 68 user I/Os handle multi-drop backplane signals and the 5V I/O tolerance matches legacy telecom -48V-isolated logic levels. The 15 ns tPD delivers the timing margin required for T1/E1 framing strobes and HDLC control signals, and the JTAG port enables in-system firmware updates without removing line cards from service. Compared with discrete TTL, a single EPM7128SLC84-15 implements 50-100 gates of bridge logic and supports last-minute protocol revisions through JTAG reprogramming.
Recommended
ASIC Prototype Logic Replacement
The EPM7128SLC84-15 functions as an ASIC prototype replacement when designers need to validate system architecture before taping out an ASIC, because the 2,500-gate capacity and JTAG-reprogrammability allow rapid architecture-iteration cycles without fab mask costs. The 15 ns tPD approximates typical ASIC gate delays, providing a realistic timing model for pre-silicon validation, while the non-volatile EEPROM ensures the prototype boots identically on every power cycle. Compared with breadboard discrete logic, the MAX 7000S shortens prototype cycles from weeks to days and provides JTAG visibility into internal nodes for debug. The 84-PLCC package also simplifies socket-swapping between prototype builds.
Recommended
Medical Device Interface Logic
The EPM7128SLC84-15 supports medical device interface-logic applications such as patient-monitor front-panel controllers, infusion-pump keypad scanners, and diagnostic-instrument display drivers, where the deterministic timing and instant-on configuration are required for FDA/IEC 62304 risk-management workflows. The 5V I/O tolerance interfaces with legacy medical-instrument analog front ends, while the JTAG-reprogrammability allows field firmware updates through validated service-port procedures. Compared with discrete CMOS logic, the integrated CPLD reduces board space for portable medical devices and simplifies IEC 60601-1 EMC compliance by consolidating many logic-edge transitions into a single controlled device.
Recommended
Test & Measurement Instrument Front End
The EPM7128SLC84-15 fits test-and-measurement instrument front-end designs such as oscilloscope trigger controllers, logic-analyzer pattern generators, and bench-top DMM range-switching logic, where the deterministic 15 ns pin-to-pin delay supports precise trigger-event timing and the 68 user I/Os handle multi-channel switching matrices. The 5V I/O tolerance interfaces with legacy op-amp signal-conditioning chains, while the JTAG-reprogrammability lets the OEM update trigger firmware over the instrument's existing service port without disassembling the chassis. Compared with discrete logic, the integrated CPLD reduces instrument front-end BOM by 30-40 percent and provides single-chip upgrade paths for new trigger features.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SLC84-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SLC84-10 | EPM7128SLC84-15N | EPM7128ELC84-20 | EPM7096LC84-15 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 84-PLCC (J84) | 84-PLCC (J84) - same | 84-PLCC (J84) - same | 84-PLCC (J84) - same | 84-PLCC (J84) - same |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E | MAX 7000 |
| Macrocells | 128 | 128 | 128 | 128 | 96 |
| User I/Os | 68 | 68 | 68 | 68 | 68 |
| Speed Grade (tPD) | 15 ns | 10 ns (faster) | 15 ns (same) | 20 ns (slower) | 15 ns (same) |
| RoHS Status | Non-RoHS (legacy SnPb) | Non-RoHS | RoHS-compliant | Non-RoHS | Non-RoHS |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG | JTAG | JTAG | JTAG |
| Approx. Unit Price (qty 1) | USD 18.50 | USD 22.00 (approx) | USD 19.50 (approx) | USD 14.00 (approx) | USD 12.00 (approx) |
Key Differentiators
- Instant-on non-volatile EEPROM configuration (no boot PROM) (vs SRAM-based FPGAs (e.g., Cyclone, Spartan families))
- 5V-tolerant multi-volt I/O directly interfaces with legacy TTL/CMOS logic (vs 3.3V-only MAX V / MAX 10 CPLDs)
- Deterministic 15 ns pin-to-pin propagation delay across all 128 macrocells (vs MAX 7000E EPM7128ELC84-20)
Design Notes
The EPM7128SLC84-15 requires a stable 5V VCCINT supply with a recommended 100 nF decoupling capacitor within 5 mm of each VCCINT pin (pins 21 and 68) and a bulk 10 uF tantalum or ceramic capacitor on the supply rail. VCCIO (pin 48) must be tied to the same 5V rail or a 3.3V rail for multi-volt I/O operation; both supplies must ramp together within 100 ms to avoid partial-configuration latch-up. The device draws approximately 150-300 mA ICC during continuous operation depending on logic-utilization and toggle rate; budget accordingly for 5V regulators.
Place all four JTAG pins (TDI pin 1, TCK pin 43, TMS pin 63, TDO pin 83) on a dedicated JTAG header with 4.7 kΩ pull-ups on TCK and TMS per IEEE 1149.1 recommendations. Keep JTAG traces short (under 50 mm) and shielded with ground pours to prevent spurious boundary-scan entry during in-system programming. If multiple MAX 7000 devices share the JTAG chain, order TDI-to-TDO carefully and ensure the chain length does not exceed the JTAG programmer's drive capability (typically 8-16 devices).
Estimated: do not assume the EPM7128SLC84-15 is bitstream-compatible with MAX 7000AE or MAX 7000E variants. Although the 84-PLCC pinout is identical across the family, the JTAG instruction-register length and ISP (in-system programming) algorithm differ between MAX 7000, MAX 7000E, and MAX 7000S. Programming a MAX 7000S image into a MAX 7000E socket (or vice versa) will fail the IDCODE verification step. Verify the device suffix matches the compiled Quartus/MAX+PLUS II project target before production programming.
Although the 84-PLCC package has modest thermal resistance (~30 C/W junction-to-ambient with socket), the 5V VCCINT combined with high internal toggle rates can produce noticeable self-heating. Estimated: at full 76.9 MHz fMAX across all 128 macrocells, internal power dissipation may reach 0.5-0.8 W, raising junction temperature by 15-25 C above ambient. For enclosed industrial enclosures without forced airflow, derate the toggle rate or specify the industrial-temperature EPM7128ELI84-20 variant for -40C to +85C operation.
Compliance Information
EPM7128SLC84-15 is the legacy SnPb (leaded) variant; the -15N suffix denotes the Pb-free RoHS-compliant version. MAX 7000 family is not AEC-Q100 qualified; this part is intended for industrial/commercial programmable-logic applications, not automotive.
