EPM7128ELC84-12 - 128-Macrocell MAX 7000 CPLD, 12ns, 84-PLCC
MPN: EPM7128ELC84-12 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.05 | $6,025.00 |
| 1,000 | $10.4 | $10,400.00 |
Drop-in alternatives for EPM7128ELC84-12 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM7128ELC84-12 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 (MAX 7000E series) |
| Logic Family | CMOS, EEPROM-based |
| Usable Gates | 2,500 |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 84 |
| Propagation Delay (tpd1) | 12 ns |
| Internal Global Clock Frequency | 90.9 MHz |
| Setup Time | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) |
| Operating Temperature | 0C to +70C (commercial) |
| Package | 84-pin PLCC (J-Lead, QCCJ) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Pin Count | 84 |
| RoHS Status | Non-compliant (legacy 5V part, SnPb finish) |
EPM7128ELC84-12 Pin Configuration
| Pin 1 | I/O β User I/O (macrocell) |
| Pin 2 | I/O β User I/O (macrocell) |
| Pin 3 | I/O β User I/O (macrocell) |
| Pin 4 | I/O β User I/O (macrocell) |
| Pin 5 | I/O β User I/O (macrocell) |
| Pin 6 | I/O β User I/O (macrocell) |
| Pin 7 | I/O β User I/O (macrocell) |
| Pin 8 | I/O β User I/O (macrocell) |
| Pin 9 | I/O β User I/O (macrocell) |
| Pin 10 | I/O β User I/O (macrocell) |
| Pin 11 | I/O β User I/O (macrocell) |
| Pin 12 | I/O β User I/O (macrocell) |
| Pin 13 | I/O β User I/O (macrocell) |
| Pin 14 | GND β Ground |
| Pin 15 | I/O β User I/O (macrocell) |
| Pin 16 | I/O β User I/O (macrocell) |
| Pin 17 | I/O β User I/O (macrocell) |
| Pin 18 | I/O β User I/O (macrocell) |
| Pin 19 | I/O β User I/O (macrocell) |
| Pin 20 | I/O β User I/O (macrocell) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (macrocell) |
| Pin 23 | I/O β User I/O (macrocell) |
| Pin 24 | I/O β User I/O (macrocell) |
| Pin 25 | I/O β User I/O (macrocell) |
| Pin 26 | I/O β User I/O (macrocell) |
| Pin 27 | I/O β User I/O (macrocell) |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O (macrocell) |
| Pin 30 | I/O β User I/O (macrocell) |
| Pin 31 | I/O β User I/O (macrocell) |
| Pin 32 | I/O β User I/O (macrocell) |
| Pin 33 | I/O β User I/O (macrocell) |
| Pin 34 | I/O β User I/O (macrocell) |
| Pin 35 | GND β Ground |
| Pin 36 | I/O β User I/O (macrocell) |
| Pin 37 | I/O β User I/O (macrocell) |
| Pin 38 | I/O β User I/O (macrocell) |
| Pin 39 | I/O β User I/O (macrocell) |
| Pin 40 | I/O β User I/O (macrocell) |
| Pin 41 | GND β Ground |
| Pin 42 | TDI β JTAG Test Data In |
| Pin 43 | TMS β JTAG Test Mode Select |
| Pin 44 | TCK β JTAG Test Clock |
| Pin 45 | TDO β JTAG Test Data Out |
| Pin 46 | GND β Ground |
| Pin 47 | I/O β User I/O (macrocell) |
| Pin 48 | I/O β User I/O (macrocell) |
| Pin 49 | I/O β User I/O (macrocell) |
| Pin 50 | I/O β User I/O (macrocell) |
| Pin 51 | I/O β User I/O (macrocell) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O (macrocell) |
| Pin 54 | I/O β User I/O (macrocell) |
| Pin 55 | I/O β User I/O (macrocell) |
| Pin 56 | I/O β User I/O (macrocell) |
| Pin 57 | I/O β User I/O (macrocell) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O (macrocell) |
| Pin 60 | I/O β User I/O (macrocell) |
| Pin 61 | I/O β User I/O (macrocell) |
| Pin 62 | I/O β User I/O (macrocell) |
| Pin 63 | I/O β User I/O (macrocell) |
| Pin 64 | GND β Ground |
| Pin 65 | I/O β User I/O (macrocell) |
| Pin 66 | I/O β User I/O (macrocell) |
| Pin 67 | I/O β User I/O (macrocell) |
| Pin 68 | I/O β User I/O (macrocell) |
| Pin 69 | I/O β User I/O (macrocell) |
| Pin 70 | I/O β User I/O (macrocell) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O (macrocell) |
| Pin 73 | I/O β User I/O (macrocell) |
| Pin 74 | I/O β User I/O (macrocell) |
| Pin 75 | I/O β User I/O (macrocell) |
| Pin 76 | I/O β User I/O (macrocell) |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O (macrocell) |
| Pin 79 | I/O β User I/O (macrocell) |
| Pin 80 | I/O β User I/O (macrocell) |
| Pin 81 | I/O β User I/O (macrocell) |
| Pin 82 | I/O β User I/O (macrocell) |
| Pin 83 | GND β Ground |
| Pin 84 | VCC β +5V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ELC84-12 is suitable for 6 applications: 5V ISA / Peripheral Bus Decoder, Industrial Control Glue Logic Replacement, Legacy VME / Multibus Interface Bridge, State-Machine Replacement for Printers and Scanners, Address Decoding / Chip-Select Generator, PCI Target Interface (5V Signaling).
5V ISA / Peripheral Bus Decoder
The EPM7128ELC84-12's 128 macrocells and 84 user I/Os make it a near-ideal replacement for dozens of 74LS TTL glue-logic chips on a 5V ISA bus decoder. The 12 ns tpd comfortably meets the ISA bus 8.33 MHz access-time budget (120 ns cycle), and the EEPROM-based architecture eliminates the boot PROM typically needed for SRAM-based FPGAs. The JTAG ISP allows field reconfiguration of chip-select logic without removing the part from its PLCC socket, and the 5V TTL I/O is directly compatible with ISA bus drivers without level translation. Engineers commonly use this part for full address decoding of memory and I/O windows, interrupt steering, and wait-state generation on legacy x86 designs.
Recommended
Industrial Control Glue Logic Replacement
In PLC backplanes and motor-drive controllers, the EPM7128ELC84-12 replaces scattered 74HC/74HCT logic with a single programmable device handling encoder decoding, PWM gating, fault latch, and watchdog timing. The 84-PLCC package is socket-friendly, allowing field replacement without rework, and the 0C to +70C commercial temperature grade suits cabinet-mounted equipment. The 5V I/O matches legacy 5V logic rails used throughout industrial PLCs, and the 90.9 MHz internal clock supports high-resolution encoder inputs. The non-volatile EEPROM configuration means the system boots into a known state within microseconds, critical for safety interlocks.
Recommended
Legacy VME / Multibus Interface Bridge
VMEbus and Multibus systems from the 1980s and 1990s still run in military, aerospace, and process-control installations, and the EPM7128ELC84-12 is widely used to bridge these 5V parallel buses to modern peripherals. The 128 macrocells provide ample logic for bus arbitration, address mapping, interrupt acknowledge daisy-chaining, and parity generation. The 12 ns tpd fits well within the VMEbus 80 ns cycle time at lower transfer rates, and the 5V TTL I/O is bus-native. The PLCC-84 package also fits in card-edge prototypes that cannot accept QFP parts.
Recommended
State-Machine Replacement for Printers and Scanners
Embedded printers, scanners, and copiers frequently use the EPM7128ELC84-12 to consolidate what would otherwise be a board full of PAL/GAL state machines into a single reprogrammable device. The 12 ns tpd easily handles the motor-control step rates of stepper and DC servo motors used in paper-handling subsystems, while the 84 I/Os cover the multiple sensors, solenoids, and optocouplers typical of such designs. The 5V operation matches the legacy 5V rails still common in printer controllers, and the EEPROM configuration survives power-cycle events that would lose SRAM-FPGA state.
Recommended
Address Decoding / Chip-Select Generator
Microprocessor systems with multiple memory and peripheral devices often need a clean chip-select generator that maps arbitrary address windows to individual CS lines. The EPM7128ELC84-12's 128 macrocells and 84 I/Os can generate up to 64 independent chip-selects with user-defined address masks and timing delays. The 12 ns tpd introduces less than one 33 MHz 486 wait-state, and the EEPROM configuration lets engineers iterate the memory map during development without board rework. This application is one of the most common MAX 7000 use-cases cited in Altera's application notes.
Recommended
PCI Target Interface (5V Signaling)
Although PCI-X and PCIe have replaced PCI in most modern designs, the original 5V PCI bus is still present in legacy industrial computers, and the EPM7128ELC84-12 can implement a complete 5V PCI target with parity, target-abort, and interrupt logic in a single device. The 12 ns tpd supports 33 MHz PCI transfers (30 ns cycle) with margin, and the 84 I/Os cover the 47-signal PCI connector plus local-bus signals. Engineers should note that 5V PCI signaling is not 3.3V-tolerant, so a level translation stage is required if the host side runs at 3.3V.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ELC84-12 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128ELC84-10 | EPM7128AELC84-10N | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC84-7 | EPM5192LC84-2 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) | 84-pin PLCC (QCCJ) |
| Family | MAX 7000E | MAX 7000E | MAX 7000AE | MAX 7000 | MAX 7000 | MAX 7000 | MAX 5000 |
| Macrocells | 128 | 128 | 128 | 96 | 96 | 96 | 192 |
| Propagation Delay (tpd1) | 12 ns | 10 ns | 10 ns | 10 ns | 15 ns | 7.5 ns | 25 ns |
| User I/Os | 84 | 84 | 84 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL |
| Approx. Unit Price (1 pc, USD) | 18.50 | 20.00 | 22.00 | 12.00 | 10.50 | 14.00 | 8.00 |
Key Differentiators
- Balanced speed/density combination for 5V logic designs (vs EPM7096LC84-10)
- More I/O pins than smaller MAX 5000 family (vs EPM5192LC84-2)
- EEPROM-based non-volatile configuration (vs SRAM-based FPGAs of the same era (e.g., FLEX 10K))
Design Notes
The EPM7128ELC84-12 requires a single 5V supply on VCC pins (pin 84 plus internal VCC pads) with multiple GND pins spread across the package for return-current integrity. Add 0.1 uF ceramic decoupling capacitors near every VCC/GND pair, and a bulk 10 uF tantalum or aluminum capacitor at the board supply input. The MAX 7000E family ICC depends on switching activity but typically ranges 100-300 mA at full speed; budget at least 500 mA for the 5V rail feeding the CPLD. Ensure the regulator maintains 4.75V-5.25V under load - drops below 4.75V cause EEPROM programming failures and unpredictable macrocell behavior.
The 84-pin PLCC J-lead package requires a PLCC-84 socket (e.g., 3M 8428-21B1 or similar) for prototype work - direct soldering is acceptable for production but field-replacement becomes difficult. Place the JTAG header (TCK/TMS/TDI/TDO/GND/VCC) within 50 mm of the device to ensure clean ISP programming; keep JTAG traces short and away from switching signals. The PLCC socket increases lead-inductance slightly versus QFP, so pay extra attention to VCC decoupling for high-toggle-rate outputs.
Do not mix 3.3V logic directly with the EPM7128ELC84-12's 5V TTL I/O - the device's input clamp diodes will forward-bias and source current back into the 3.3V driver, potentially damaging both parts. Use a dedicated level translator (74LVC245, TXS0108E) when interfacing to 3.3V peripherals. Also note that the MAX 7000E JTAG chain order is fixed by silicon; if multiple CPLDs share a JTAG chain, enable BYPASS in the Quartus II device options. Finally, the -12 speed grade's 12 ns tpd is a worst-case commercial-grade specification - derate additional margin for industrial-temperature operation if migrating to the -15 grade.
Keep all user-I/O traces within 50 mm and route them over a continuous ground plane for best signal integrity. For high-speed outputs (>50 MHz toggle rate), add 33 ohm series-termination resistors to dampen reflections on long traces. The PLCC-84 package has ground pins distributed around the perimeter; stitch the top and bottom ground planes together with vias placed within 5 mm of each GND pin for low-inductance return paths.
Compliance Information
The EPM7128ELC84-12 is a legacy Altera/Intel 5V CPLD with SnPb (lead-tin) finish - explicitly non-RoHS per Altera's legacy product documentation. The original datasheet states lead-based termination plating. REACH compliance is unknown / not declared for this EOL part. AEC-Q100 is not applicable (industrial/consumer grade only, no automotive qualification).
