EPM7128SLI84-10N vs EPM7128SLC84-7N Comparison
Detailed side-by-side comparison of EPM7128SLI84-10N by Altera and EPM7128SLC84-7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SLI84-10N
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndIntel
EPM7128SLC84-7N
EPM7128SLC84-7N - 128 Macro Cell 7.5ns MAX 7000S CPLD | Intel
EPM7128SLC84-7N ObsoleteSpecification Comparison
| Parameter | EPM7128SLI84-10N | EPM7128SLC84-7N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.45 | $8.75 |
| Family | MAX 7000S | β |
| Logic Cells / Macro Cells | 128 macro cells | β |
| Usable Gates | 2,500 | β |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | β |
| User I/Os | 68 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Frequency (fMAX) | 125 MHz | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | β |
| Process Technology | CMOS EEPROM | β |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | β |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | β |
| Package | 84-pin PLCC (J-Lead) | 84-LCC (J-Lead), PLCC-84 |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | β |
| Series | β | MAX 7000S |
| Programmable Type | β | In System Programmable (ISP) |
| Memory Type | β | EEPROM |
| Number of Macrocells | β | 128 |
| Number of Logic Elements/Blocks | β | 8 (Logic Array Blocks) |
| Number of Usable Gates | β | 2,500 |
| Number of I/O Pins | β | 68 |
| Propagation Delay (tpd) Max | β | 7.5 ns |
| Maximum Operating Frequency | β | 125 MHz |
| Counter Speed (Internal) | β | up to 175.4 MHz (family max) |
| MSL Level | β | [DATA_NEEDED: MSL level] |