EPM7128SLI84-10N vs EPM7128SLC84-7N Comparação
Comparação detalhada lado a lado de EPM7128SLI84-10N por Altera e EPM7128SLC84-7N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndComparação de especificações
| Parâmetro | EPM7128SLI84-10N | EPM7128SLC84-7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,45 | $8,75 |
| Family | MAX 7000S | — |
| Logic Cells / Macro Cells | 128 macro cells | — |
| Usable Gates | 2,500 | — |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| User I/Os | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | — |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | — |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Encapsulamento | 84-pin PLCC (J-Lead) | 84-LCC (J-Lead), PLCC-84 |
| Tipo de montagem | Surface Mount | Surface Mount |
| Temperatura de operação | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | — |
| Series | — | MAX 7000S |
| Programmable Type | — | In System Programmable (ISP) |
| Tipo de memória | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Elements/Blocks | — | 8 (Logic Array Blocks) |
| Number of Usable Gates | — | 2,500 |
| Number of I/O Pins | — | 68 |
| Propagation Delay (tpd) Max | — | 7.5 ns |
| Maximum Operating Frequency | — | 125 MHz |
| Counter Speed (Internal) | — | up to 175.4 MHz (family max) |
| Nível MSL | — | [DATA_NEEDED: MSL level] |