EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
MPN: EPM7128SLI84-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 250 | $9.1 | $2,275.00 |
| 500 | $8.45 | $4,225.00 |
Drop-in alternatives for EPM7128SLI84-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128SLI84-10
✅ Drop-In✓ In Stock
$7.25 / Unit
View Datasheet →EPM7128SLC84-10
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPM7128SLC84-10N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128SLC84-6N
✅ Drop-In✓ In Stock
$8.75 / Unit
View Datasheet →EPM7128SLC84-7N
✅ Drop-In✓ In Stock
$8.75 / Unit
View Datasheet →EPM7128SLC84-15
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EPM7128ELI84-20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPM7128SLI84-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Logic Cells / Macro Cells | 128 macro cells |
| Usable Gates | 2,500 |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) |
| User I/Os | 68 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency (fMAX) | 125 MHz |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | CMOS EEPROM |
| Programmability | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant |
| Package | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 C to +85 C (Industrial) |
EPM7128SLI84-10N 84-pin plcc (j-lead) Pin Configuration Guide
Complete pinout information for EPM7128SLI84-10N (84-pin plcc (j-lead) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM7128SLI84-10N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SLI84-10N is suitable for 6 applications: PCI / ISA Bus Decoder and Chip-Select Glue Logic, Industrial 5 V State-Machine Controllers, Legacy PAL / GAL Device Replacement and Consolidation, VME / VXS Backplane Address Decoding, In-System Programmable (ISP) Peripheral Hub, Medical Imaging and Diagnostic Equipment I/O Expansion.
PCI / ISA Bus Decoder and Chip-Select Glue Logic
The EPM7128SLI84-10N is a textbook choice for legacy PCI and ISA bus decoding in industrial single-board computers and embedded controllers. Its 10 ns pin-to-pin propagation delay comfortably meets the 33 MHz PCI clock-to-output timing requirement, and the 68 user I/Os accommodate the wide address and control buses (AD31:0 plus C/BE3:0 plus FRAME/IRDY/TRDY/DEVSEL) needed for full 32-bit decoder logic. The 5 V MultiVolt I/O bank allows direct interface to 5 V ISA peripherals without level shifters, and the 128 macro cells provide ample product-term capacity for combined address decoding plus interrupt acknowledge logic. Place the CPLD between the system controller and the backplane connectors, with the JTAG chain accessible for in-field firmware updates via Altera's MAX+PLUS II or Quartus II programmer.
Recommended
Industrial 5 V State-Machine Controllers
The EPM7128SLI84-10N's non-volatile EEPROM configuration makes it ideal for industrial state-machine controllers that must power up in a deterministic, known state - critical for machine-tool interlocks, conveyor sequencing, and process-control valve actuation. The industrial -40 C to +85 C operating range (denoted by the "I" suffix) handles factory-floor temperature swings, while the 128 macro cells and 16 LABs comfortably implement 8-16 state finite state machines with combinational pre-decoders. The 5 V core allows direct drive of industrial 24 V optically-isolated I/O via external high-side switches, eliminating the level-shift stage required by 3.3 V CPLDs.
Recommended
Legacy PAL / GAL Device Replacement and Consolidation
The EPM7128SLI84-10N is the canonical upgrade path for board designs that previously used multiple 22V10, 26V12, or 16L8 PAL/GAL devices to implement address decoding, bus arbitration, and custom I/O mapping. A single MAX 7128 CPLD can replace 4-8 discrete PAL/GALs, reducing PCB area, power consumption, and inventory SKU count. The MAX+PLUS II and Quartus II design tools accept standard CUPL, ABEL, and PALASM source code, allowing legacy designs to migrate with minimal re-synthesis effort. The non-volatile EEPROM configuration means the replacement board behaves identically to the original PAL design at power-up with no bootloader or configuration PROM.
Recommended
VME / VXS Backplane Address Decoding
In VMEbus and VXS (VITA 41) backplane applications, the EPM7128SLI84-10N provides the 32-bit address decoding, interrupt acknowledge (IACK) daisy-chain driver, and bus-request/grant arbitration logic that defines a VME master or slave slot. The 10 ns tPD comfortably meets the 8 ns VMEbus signal-to-acknowledge timing, and the 68 user I/Os map directly to the VME P1/J1 connector pinout for address (A31:A01), data strobes (DS0, DS1), and the AM0-AM5 address-modifier lines. The 5 V tolerance is mandatory because VMEbus is a 5 V signaling standard.
Recommended
In-System Programmable (ISP) Peripheral Hub
The EPM7128SLI84-10N's JTAG-compliant IEEE 1149.1 boundary-scan interface enables in-system programming without removing the device from the board - a major advantage for field-deployed equipment where device-swap rework is costly. Designers can implement a custom peripheral hub that aggregates 4-8 UART, SPI, or GPIO peripherals onto a single processor bus, with the CPLD's behavior updated over JTAG to add new peripheral protocols as firmware features grow. The 128 macro cells easily absorb 32-bit register-file decode plus interrupt-aggregation logic, and the 5 V I/O bank interfaces directly to RS-232 / RS-485 line drivers without external level translation.
Recommended
Medical Imaging and Diagnostic Equipment I/O Expansion
The EPM7128SLI84-10N is used in medical imaging carts, ultrasound front-ends, and patient-monitor chassis as a deterministic, low-latency I/O expansion layer between the main CPU and specialized medical peripherals (Doppler probes, ECG front-ends, SpO2 modules). Its 10 ns tPD supports the deterministic timing needed for medical-grade sampling-rate synchronization, and the -40 C to +85 C industrial temperature range accommodates the warm operating environment inside sealed medical-device enclosures. The non-volatile configuration ensures the device powers up in a known safe state - a regulatory requirement under IEC 60601-1 for medical electrical equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SLI84-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SLI84-10 | EPM7128SLC84-10 | EPM7128SLC84-6N | EPM7128SLC84-7N |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Family | MAX 7000S (5 V) | MAX 7000S (5 V) | MAX 7000S (5 V) | MAX 7000S (5 V) | MAX 7000S (5 V) |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 6 ns | 7.5 ns |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 68 | 68 | 68 | 68 | 68 |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) |
| Core Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Industrial -40 C to +85 C temperature range (vs EPM7128SLC84-10N)
- Balanced 10 ns speed / cost ratio (vs EPM7128SLC84-6N)
- True PLCC-84 drop-in for legacy board repair (vs MAX II EPM240T100C5N)
Design Notes
Estimated: At VCC = 5.0 V and ICC(active) approximately 100 mA (typical for MAX 7000S with 128 cells active), worst-case power dissipation is approximately 0.5 W. The PLCC-84 package has a typical theta_JA of approximately 35 C/W in still air, yielding a junction-temperature rise of about 17 C above ambient - well within the 125 C junction limit. For commercial chassis (ambient 50 C), no heatsink is required. For each I/O pin switching at 10 MHz with 50 pF load, add approximately 25 mW of dynamic I/O power; budget total worst-case I/O power as N x 0.025 W where N is the number of active switching outputs.
Place one 0.1 uF X7R ceramic decoupling capacitor within 5 mm of every VCC pin pair (the PLCC-84 has 4 VCC and 4 GND pins distributed around the package periphery). Add one bulk 10 uF tantalum or low-ESR ceramic on each side of the package to handle simultaneous-switching-output (SSO) current transients. Per Altera AN 74 (MAX 7000 In-System Programmability), the JTAG chain TMS, TCK, TDI, TDO pins should be pulled up to VCC through 10 kohm resistors if the JTAG interface is not used, to prevent floating CMOS inputs. Trace the JTAG chain in a daisy-chain topology with TCK distributed via a clock buffer if more than 3 devices share the chain.
Three common pitfalls when designing with the EPM7128SLI84-10N: (1) Do not assume the -10N speed grade is adequate for 66 MHz PCI - if your design targets 66 MHz PCI, use the -6 or -7 grade; the 10 ns delay is borderline for 66 MHz and forces zero-margin timing closure. (2) The "S" (MAX 7000S, 5 V) and "E" (MAX 7000A, 3.3 V) variants are NOT drop-in compatible at the power rail - swapping an S for an E on a 5 V board will release the magic smoke within milliseconds. (3) NRND status means last-time-buy windows close without notice - place LTBs now if you need multi-year production support, and qualify the MAX II EPM240 as a second-source path.
Compliance Information
RoHS/REACH/lead-free status for the EPM7128SLI84-10N is [DATA_NEEDED] - Intel/Altera legacy MAX 7000 PLCC-84 parts are commonly supplied in non-RoHS SnPb finish; verify the latest material declaration with Intel FPGA product compliance before placing production orders. AEC-Q100 is not_applicable (this is a commercial/industrial CPLD, not an automotive-grade part).
