EPM7128SQC100-10 vs EPM7128SQC100-7N Comparison
Detailed side-by-side comparison of EPM7128SQC100-10 by Altera and EPM7128SQC100-7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-10 | EPM7128SQC100-7N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| Logic Elements / Gates | 2,500 usable gates | — |
| Maximum User I/O | 84 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Supply Voltage | 5 V | — |
| Process Technology | 5V CMOS, EEPROM-based | 0.30 µm CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (QFP-100) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | Compliant (lead-free 'N' suffix) |
| Program Memory Type | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macrocell | — | 32 |
| Usable Gates | — | 2,500 |
| System Gates | — | 5,000 (max) |
| Maximum User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Counter Speed | — | 175.4 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | — | 5.0 V |
| I/O Standard Support | — | multiVolt (2.5V, 3.3V, 5.0V) |
| Security Bit | — | Programmable (one per device) |