EPM7128STC100-10N vs EPM7128AETC100-10N Comparison
Detailed side-by-side comparison of EPM7128STC100-10N by Altera and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-10N
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndIntel
EPM7128AETC100-10N
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-10N | EPM7128AETC100-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.30 | $9.95 |
| Family | MAX 7000S | MAX 7000AE |
| Product Type | CPLD - Complex Programmable Logic Device | β |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | β |
| User I/Os | 84 | 84 |
| Propagation Delay (tPD) | 10 ns | β |
| Internal Frequency (fMAX) | 100 MHz | β |
| Supply Voltage (VCCINT) | 5 V | β |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Package | 100-pin TQFP (14 x 14 x 1 mm) | TQFP-100 |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (Pb-free "N" suffix) | β |
| Lead-Free | Yes | β |
| Series | β | EPM7128AE |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | β | 16 |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Tolerance | β | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Speed Grade | β | -10 |
| Maximum Frequency | β | [DATA_NEEDED: maximum toggle frequency] |
| Programming | β | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Architecture | β | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | β | Yes (33 MHz, -10 grade per PCI SIG 2.2) |