EPM7128STC100-10N vs EPM7128AETI100-7N Comparison
Detailed side-by-side comparison of EPM7128STC100-10N by Altera and EPM7128AETI100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndAltera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-10N | EPM7128AETI100-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000A CPLD |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| User I/Os | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 3.0 V to 3.6 V |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Package | 100-pin TQFP (14 x 14 x 1 mm) | 100-pin TQFP (14x14 mm) |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (Industrial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (JTAG IEEE 1149.1) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (Pb-free "N" suffix) | Compliant |
| Lead-Free | Yes | — |
| Series | — | MAX 7000A |
| Macro Cells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |