EPM7128STC100-6N vs EPM7128AETC100-7N Comparison
Detailed side-by-side comparison of EPM7128STC100-6N by Altera and EPM7128AETC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-6N | EPM7128AETC100-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000A |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | 84 |
| Logic Family | CMOS | CMOS |
| Number of Pins | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | — |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | — |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | — |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM CMOS |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Operating Temperature | 0C to +70C (Commercial) | 0 C to +70 C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-Compliant (lead-bearing package) | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tpd) | — | 7.5 ns |
| Counter Frequency (max) | — | 129.9 MHz |
| Internal Frequency (max) | — | 250 MHz |
| Core Supply Voltage | — | 3.3 V |
| Pin Count | — | 100 |
| Package | — | 100-TQFP |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |