EPM7128STC100-6N vs EPM7128AETC100-7N 对比
详细并排对比 EPM7128STC100-6N 出自 Altera 和 EPM7128AETC100-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N Obsolete规格对比
| 参数 | EPM7128STC100-6N | EPM7128AETC100-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.50 | $31.80 |
| Family | MAX 7000S | MAX 7000A |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | 84 |
| Logic Family | CMOS | CMOS |
| 引脚数 | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | — |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | — |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | — |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM CMOS |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| 工作温度 | 0C to +70C (Commercial) | 0 C to +70 C (Commercial) |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | Non-Compliant (lead-bearing package) | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tpd) | — | 7.5 ns |
| Counter Frequency (max) | — | 129.9 MHz |
| Internal Frequency (max) | — | 250 MHz |
| Core Supply Voltage | — | 3.3 V |
| 引脚数量 | — | 100 |
| 封装 | — | 100-TQFP |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |