EPM7128STC100-6N vs EPM7128STC100-10N Comparison
Detailed side-by-side comparison of EPM7128STC100-6N by Altera and EPM7128STC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteAltera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndSpecification Comparison
| Parameter | EPM7128STC100-6N | EPM7128STC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $9.30 |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | β |
| User I/Os | 84 | 84 |
| Logic Family | CMOS | β |
| Number of Pins | 100 | β |
| Package Type | TQFP-100 | β |
| Maximum Internal Frequency | 147.1 MHz | β |
| Internal Counter Frequency | 250 MHz | β |
| Propagation Delay (tPD) | 6 ns | 10 ns |
| Pin-to-Pin Delay | 4.5 ns | β |
| Supply Voltage (VCCIO) | 5 V | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| JTAG Support | IEEE 1149.1 Boundary Scan | β |
| Operating Temperature | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-Compliant (lead-bearing package) | Compliant (Pb-free "N" suffix) |
| Product Type | β | CPLD - Complex Programmable Logic Device |
| Macrocells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 (16 macrocells each) |
| Internal Frequency (fMAX) | β | 100 MHz |
| Supply Voltage (VCCINT) | β | 5 V |
| I/O Voltage (VCCIO) | β | 3.3 V or 5 V (MultiVolt) |
| Package | β | 100-pin TQFP (14 x 14 x 1 mm) |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Lead-Free | β | Yes |