EPM7128STC100-6N vs EPM7128STC100-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-6N disebabkan oleh Altera dan EPM7128STC100-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteAltera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndPengandingan Spesifikasi
| Parametr | EPM7128STC100-6N | EPM7128STC100-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | — |
| User I/Os | 84 | 84 |
| Logic Family | CMOS | — |
| Bilangan Pin | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | — |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | 10 ns |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Suhu Operasi | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | Non-Compliant (lead-bearing package) | Compliant (Pb-free "N" suffix) |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| Internal Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (MultiVolt) |
| Kemasan | — | 100-pin TQFP (14 x 14 x 1 mm) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Lead-Free | — | Yes |