EPM7160SLC84-10 vs EPM7160ELC84-15 Comparison
Detailed side-by-side comparison of EPM7160SLC84-10 by Altera and EPM7160ELC84-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7160SLC84-10 | EPM7160ELC84-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 64 | — |
| Usable Gates | 3,200 | 3,200 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | Yes (IEEE 1149.1 JTAG) |
| Technology | EEPROM-based CMOS | — |
| Package | 84-Pin PLCC (J-Lead) | — |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Contains lead / RoHS non-compliant (per Altera listing) |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| Architecture | — | EEPROM-based, second-generation MAX |
| Logic Array Blocks | — | 4 |
| Maximum I/O Pins | — | 36 |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Frequency | — | 76.9 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Package Type | — | 84-pin PLCC (J-Lead) |