EPM7160ELC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns, 84-PLCC
MPN: EPM7160ELC84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.85 | $78.50 |
| 100 | $7 | $700.00 |
| 300 | $6.59 | $1,977.00 |
| 1,000 | $5.95 | $5,950.00 |
Drop-in alternatives for EPM7160ELC84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160SLC84-10
β Drop-Inβ In Stock
$35.77 / Unit
View Datasheet βEPM7160SLC84-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7160SLC84-6
β Drop-Inβ In Stock
$15.86 / Unit
View Datasheet βEPM7160ELC84-12
β Drop-Inβ In Stock
$11.1 / Unit
View Datasheet βEPM7160ELC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELI84-20
β Drop-Inβ In Stock
$11.1 / Unit
View Datasheet βEPM7160ELI84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Product Type | CPLD - Complex Programmable Logic Device |
| Architecture | EEPROM-based, second-generation MAX |
| Usable Gates | 3,200 |
| Macrocells | 160 |
| Logic Array Blocks | 4 |
| Maximum I/O Pins | 36 |
| Pin-to-Pin Delay | 15 ns |
| Counter Frequency | 76.9 MHz |
| Supply Voltage (Vcc) | 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Package Type | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0 C to +70 C (commercial) |
| RoHS Status | Contains lead / RoHS non-compliant (per Altera listing) |
EPM7160ELC84-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell) |
| Pin 2 | I/O β User I/O pin (macrocell) |
| Pin 3 | I/O β User I/O pin (macrocell) |
| Pin 4 | I/O β User I/O pin (macrocell) |
| Pin 5 | I/O β User I/O pin (macrocell) |
| Pin 6 | I/O β User I/O pin (macrocell) |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β User I/O pin (macrocell) |
| Pin 9 | I/O β User I/O pin (macrocell) |
| Pin 10 | I/O β User I/O pin (macrocell) |
| Pin 11 | I/O β User I/O pin (macrocell) |
| Pin 12 | I/O β User I/O pin (macrocell) |
| Pin 13 | I/O β User I/O pin (macrocell) |
| Pin 14 | GND β Ground |
| Pin 15 | I/O β User I/O pin (macrocell) |
| Pin 16 | I/O β User I/O pin (macrocell) |
| Pin 17 | I/O β User I/O pin (macrocell) |
| Pin 18 | I/O β User I/O pin (macrocell) |
| Pin 19 | I/O β User I/O pin (macrocell) |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin (macrocell) |
| Pin 22 | I/O β User I/O pin (macrocell) |
| Pin 23 | I/O β User I/O pin (macrocell) |
| Pin 24 | I/O β User I/O pin (macrocell) |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O pin (macrocell) |
| Pin 27 | I/O β User I/O pin (macrocell) |
| Pin 28 | I/O β User I/O pin (macrocell) |
| Pin 29 | I/O β User I/O pin (macrocell) |
| Pin 30 | I/O β User I/O pin (macrocell) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (macrocell) |
| Pin 33 | I/O β User I/O pin (macrocell) |
| Pin 34 | I/O β User I/O pin (macrocell) |
| Pin 35 | I/O β User I/O pin (macrocell) |
| Pin 36 | I/O β User I/O pin (macrocell) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (macrocell) |
| Pin 39 | I/O β User I/O pin (macrocell) |
| Pin 40 | I/O β User I/O pin (macrocell) |
| Pin 41 | I/O β User I/O pin (macrocell) |
| Pin 42 | I/O β User I/O pin (macrocell) |
| Pin 43 | GND β Ground |
| Pin 44 | I/O β User I/O pin (macrocell) |
| Pin 45 | I/O β User I/O pin (macrocell) |
| Pin 46 | I/O β User I/O pin (macrocell) |
| Pin 47 | I/O β User I/O pin (macrocell) |
| Pin 48 | I/O β User I/O pin (macrocell) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin (macrocell) |
| Pin 51 | I/O β User I/O pin (macrocell) |
| Pin 52 | I/O β User I/O pin (macrocell) |
| Pin 53 | I/O β User I/O pin (macrocell) |
| Pin 54 | I/O β User I/O pin (macrocell) |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin (macrocell) |
| Pin 57 | I/O β User I/O pin (macrocell) |
| Pin 58 | I/O β User I/O pin (macrocell) |
| Pin 59 | I/O β User I/O pin (macrocell) |
| Pin 60 | I/O β User I/O pin (macrocell) |
| Pin 61 | GND β Ground |
| Pin 62 | INPUT/GCLK β Global clock / dedicated input pin |
| Pin 63 | INPUT/OE1 β Global output enable / dedicated input |
| Pin 64 | INPUT/OE2/GCLK2 β Secondary global clock / output enable / dedicated input |
| Pin 65 | TDI β JTAG Test Data In (MAX 7000S only) |
| Pin 66 | TMS β JTAG Test Mode Select (MAX 7000S only) |
| Pin 67 | TCK β JTAG Test Clock (MAX 7000S only) |
| Pin 68 | NC β Not connected (per datasheet) |
| Pin 69 | NC β Not connected (per datasheet) |
| Pin 70 | NC β Not connected (per datasheet) |
| Pin 71 | NC β Not connected (per datasheet) |
| Pin 72 | NC β Not connected (per datasheet) |
| Pin 73 | NC β Not connected (per datasheet) |
| Pin 74 | TDO β JTAG Test Data Out (MAX 7000S only) |
| Pin 75 | VCC β 5.0V supply |
| Pin 76 | VCC β 5.0V supply |
| Pin 77 | VCC β 5.0V supply |
| Pin 78 | VCC β 5.0V supply |
| Pin 79 | VCC β 5.0V supply |
| Pin 80 | VCC β 5.0V supply |
| Pin 81 | VCC β 5.0V supply |
| Pin 82 | VCC β 5.0V supply |
| Pin 83 | VCC β 5.0V supply |
| Pin 84 | VCC β 5.0V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160ELC84-15 is suitable for 6 applications: Legacy 5V Bus Address Decoding, Glue Logic Replacement (74LS/74HC TTL Consolidation), Industrial Control and Instrumentation, Telecommunications Line Cards and Backplane Bridging, Military and Aerospace Long-Life Programs, Peripheral Bridging and Interface Adaptation.
Legacy 5V Bus Address Decoding
The EPM7160ELC84-15 fits legacy 5-V address decoding because it operates directly from a 5 V rail without level translation, and its 15 ns pin-to-pin delay comfortably meets ISA, VME, and STD-bus timing budgets. With 160 macrocells it can hold dozens of independent decode windows (chip-select, memory map, interrupt acknowledge), consolidating what previously required multiple 74LS138/688 PLD pairs onto one PLCC84 device.
Recommended
Glue Logic Replacement (74LS/74HC TTL Consolidation)
The EPM7160ELC84-15 is well-suited for replacing dozens of 74LS/74HC glue-logic packages because its 160 macrocells absorb SSI/MSI functions (decoders, muxes, latches, simple state machines) into a single PLCC84 device. The 5 V tolerance means it interfaces directly to legacy TTL outputs, and its deterministic 15 ns propagation delay preserves the timing relationships the original TTL design depended on, simplifying BOM and PCB rework.
Recommended
Industrial Control and Instrumentation
Industrial control and instrumentation uses the EPM7160ELC84-15 as the deterministic glue logic between microcontrollers, ADCs, DACs, display drivers, and motor-control peripherals. Its 5 V CMOS I/O is noise-tolerant on long cable runs, the 84-pin PLCC package withstands industrial thermal cycling, and 160 macrocells accommodate multi-channel state machines for sequential valve/relay control. The commercial 0-70 C grade suits cabinet-mounted equipment; use the -ELI84 industrial variant for harsher environments.
Recommended
Telecommunications Line Cards and Backplane Bridging
The EPM7160ELC84-15 suits telecom line cards and backplane bridging because its 160 macrocells absorb protocol-format conversion (HDB3/AMI/8B10B framing), clock-domain crossing, and bus-arbitration state machines in one non-volatile device. The 5 V tolerance is native to legacy T1/E1 line interfaces, and the 76.9 MHz counter frequency cleanly handles sub-100 MHz system clocks. JTAG boundary-scan on the MAX 7000S variant accelerates board-level fault isolation.
Recommended
Military and Aerospace Long-Life Programs
The EPM7160ELC84-15 remains in service for military and aerospace long-life programs because MAX 7000 CPLDs are non-volatile (EEPROM configuration is retained without external boot memory), deterministic in timing, and supported through Intel PSG's long-term product programs. The 84-pin PLCC package tolerates conformal coating and rework, and obsolete parts flow through franchised brokers with full traceability, which is essential for DO-254 and MIL-HDBK-454 compliance documentation.
Recommended
Peripheral Bridging and Interface Adaptation
The EPM7160ELC84-15 is well suited for peripheral bridging and interface adaptation (e.g. parallel-bus to SPI, ISA to memory-mapped peripheral, or async SRAM to synchronous controller). Its 160 macrocells hold wide datapath muxes, the 5 V I/O bank mates with 3.3 V devices through simple resistive dividers, and the 15 ns Tpd fits the timing requirements of 33 MHz peripheral buses without inserting wait states.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160ELC84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10 | EPM7160SLC84-7 | EPM7160SLC84-6 | EPM7160ELC84-12 | EPM7160ELC84-10 | EPM7160ELI84-20 | EPM7160ELI84-10 |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Pin-to-Pin Delay (Tpd) | 15 ns | 10 ns (-33%) | 7.5 ns (-50%) | 6 ns (-60%) | 12 ns (-20%) | 10 ns (-33%) | 20 ns (+33%) | 10 ns (-33%) |
| Counter Frequency (Fcnt) | 76.9 MHz | 100 MHz | 125 MHz | 151 MHz | 83.3 MHz | 100 MHz | 76.9 MHz | 100 MHz |
| Supply Voltage | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same |
| Temperature Range | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| In-System Programming (JTAG) | No (MAX 7000E - parallel only) | Yes (MAX 7000S) | Yes (MAX 7000S) | Yes (MAX 7000S) | No | No | No | No |
Key Differentiators
- Same PLCC84 footprint as MAX 7000S JTAG-ISP variants (vs EPM7160SLC84-10)
- Three speed-grade upgrades available in the same package (vs EPM7160SLC84-7 / EPM7160SLC84-6)
- Industrial-temperature variants available for harsher environments (vs EPM7160ELI84-10 / EPM7160ELI84-20)
Design Notes
Estimated: at Vcc = 5.0 V and a typical Icc of 250 mA (commercial, all I/O switching at 76.9 MHz), the EPM7160ELC84-15 dissipates approximately 1.25 W. Use a 4-layer PCB with a continuous ground plane under the PLCC and at least 8 Vcc/GND pin pairs decoupled with 0.1 uF X7R ceramic capacitors placed within 3 mm of each Vcc pin. Add one bulk 10 uF tantalum or aluminum polymer capacitor at the board supply entry. The 'E' (5-V) supply must be regulated within +/- 10% (4.5 V to 5.5 V); exceeding 5.5 V will stress the EEPROM cells and may corrupt configuration.
The 84-pin PLCC J-lead package requires a land pattern per JEDEC MS-018 with 1.27 mm pitch. Recommended reflow profile follows JEDEC J-STD-020 (peak 235 C for SnPb, since this part is lead-bearing). For prototype work, use a through-hole PLCC84 socket (e.g. 3M Textool) so devices can be reprogrammed and replaced. Place all decoupling capacitors on the same PCB side as the CPLD and route Vcc/GND pairs in parallel, never daisy-chained, to keep supply inductance below 1 nH per pin.
Common pitfalls: (1) Don't assume the EPM7160ELC84-15 has JTAG ISP - it is a MAX 7000E (parallel programmable) variant; for JTAG ISP choose the EPM7160SLC84-10 or faster SLC speed grades. (2) Don't exceed 7 mA per I/O DC sink/source or you will degrade the output Voh/Vol levels. (3) Configure all unused I/O pins as outputs driving low (per Altera Quartus / MAX+PLUS II defaults) to minimize Icc standby. (4) When migrating from 74LS/74HC, derate your worst-case propagation delay calculation by 10% to account for I/O buffer variation across temperature.
Compliance Information
Altera listing explicitly states 'Contains lead / RoHS non-compliant'. The MAX 7000 family is fabricated on a 5-V CMOS EEPROM process; not qualified to AEC-Q100 (automotive). REACH and conflict-minerals status not disclosed in available data.
