EPM7160SLC84-10 - 160-Macrocell MAX 7000S CPLD | Altera
MPN: EPM7160SLC84-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $59.62 | $59.62 |
| 10 | $53.66 | $536.60 |
| 100 | $47.7 | $4,770.00 |
| 500 | $41.73 | $20,865.00 |
| 1,000 | $35.77 | $35,770.00 |
Drop-in alternatives for EPM7160SLC84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160SLC84-10N
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7160ELC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELI84-20
β Drop-Inβ In Stock
$11.1 / Unit
View Datasheet βEPM7128SLC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.75 / Unit
View Datasheet βEPM7128ELC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.2 / Unit
View Datasheet βEPM7160SLC84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Macrocells | 160 |
| Logic Array Blocks (LABs) | 4 |
| Maximum User I/O Pins | 64 |
| Usable Gates | 3,200 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| Technology | EEPROM-based CMOS |
| Package | 84-Pin PLCC (J-Lead) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) |
EPM7160SLC84-10 Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | TDI β JTAG Test Data In |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | VCC β +5V supply |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | TMS β JTAG Test Mode Select |
| Pin 34 | VCC β +5V supply |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | TCK β JTAG Test Clock |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | VCC β +5V supply |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | GND β Ground |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | TDO β JTAG Test Data Out |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SLC84-10 is suitable for 6 applications: 5V Industrial Glue Logic, Microprocessor Address Decoding, Legacy Telecom Backplane Interface, PCI/ISA Bus Arbitration, State Machine and Sequencer Replacement, Prototype and Educational FPGA/CPLD Platform.
5V Industrial Glue Logic
The EPM7160SLC84-10's 5V-tolerant I/O and 160 macrocells make it ideal for replacing multiple 74-series logic ICs in industrial control boards, reducing BOM count and PCB area. Its deterministic 10 ns tPD ensures reliable decoding and arbitration across industrial 5V backplanes. Designers typically use Quartus II or MAX+PLUS II to capture the logic, then program via JTAG on-board.
Recommended
Microprocessor Address Decoding
The EPM7160SLC84-10 is widely deployed for memory and peripheral address decoding in 5V 8051, 68k, and PowerPC designs where deterministic 10 ns timing avoids wait-state insertion. Its 64 user I/Os handle 24-bit address plus chip-select distribution, and its 5V tolerance mates directly with 5V SRAM, Flash, and peripheral buses. The device reduces decode-glue from dozens of 74LS138/139 chips to one CPLD.
Recommended
Legacy Telecom Backplane Interface
Telecom backplanes using 5V H.110 or similar buses benefit from the EPM7160SLC84-10's JTAG ISP, 160 macrocells, and 100 MHz internal frequency for clock distribution and bus arbitration. The 84-pin PLCC socket-friendly package allows field-replaceable modules in legacy central-office equipment. Designers use the device for serial-to-parallel conversion and time-slot management.
Recommended
PCI/ISA Bus Arbitration
The EPM7160SLC84-10 implements deterministic bus arbitration logic in legacy PCI/ISA systems where single-cycle 10 ns response is mandatory. Its 64 I/Os accept address, command, and grant signals from multiple bus masters, while its 5V tolerance matches the legacy 5V PCI signaling environment. The JTAG ISP allows post-assembly reconfiguration of arbitration priorities.
Recommended
State Machine and Sequencer Replacement
The EPM7160SLC84-10 replaces discrete state-machine PALs and 74LS-series sequencers in 5V embedded control systems, integrating dozens of small programmable devices into a single 84-pin PLCC. Designers port existing PAL equations directly into MAX+PLUS II, retaining exact timing. Its 160 macrocells and 100 MHz fMAX handle multi-state power-up and fault-recovery sequencers.
Recommended
Prototype and Educational FPGA/CPLD Platform
The EPM7160SLC84-10 is popular in university digital-logic labs and hobbyist projects because the 84-pin PLCC fits low-cost sockets, and Altera's MAX+PLUS II (free student edition) supports the device. Students learn VHDL/Verilog design entry, JTAG programming, and timing analysis on a real 5V CPLD. The 160-macrocell capacity exercises non-trivial designs without the cost of larger FPGAs.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SLC84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10N | EPM7160ELC84-10 | EPM7160ELI84-20 | EPM7128SLC84-10 | EPM7128ELC84-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead) |
| Macrocells | 160 | 160 | 160 | 160 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 20 ns | 10 ns | 10 ns |
| Family | MAX 7000S | MAX 7000S | MAX 7000AE | MAX 7000AE | MAX 7000S | MAX 7000AE |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| RoHS Compliance | [DATA_NEEDED] | Yes (lead-free) | Yes | Yes | [DATA_NEEDED] | Yes |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| JTAG ISP | Yes (5.0 V) | Yes (5.0 V) | Yes (5.0 V) | Yes (5.0 V) | Yes (5.0 V) | Yes (5.0 V) |
Key Differentiators
- Highest-density MAX 7000S in PLCC-84 footprint (vs EPM7128SLC84-10)
- Lower power consumption vs MAX 7000S (vs EPM7160ELC84-10)
- Industrial temperature range option (vs EPM7160ELI84-20)
Design Notes
The EPM7160SLC84-10 operates from a single 5.0V supply. According to the MAX 7000S datasheet, VCC must rise monotonically during power-up; non-monotonic ramps can cause improper JTAG initialization or programming failure. Use a supervisor IC or well-decoupled regulator to guarantee monotonic 5V rise. Decoupling: place 0.1uF ceramic capacitors within 5 mm of every VCC pin and a bulk 10uF tantalum near the device.
The 84-pin PLCC J-Lead package has a JEDEC-standard 1.27 mm pitch. Provide a continuous ground plane on the layer beneath the device to reduce EMI. Keep JTAG TDI/TDO/TMS/TCK traces short and parallel; add 10k pull-ups on TMS and TDI per IEEE 1149.1 recommendations. Leave space around the device for a PLCC test socket if the design is a prototype.
Common design pitfalls: (1) Forgetting that MAX 7000S devices require a 5V ISP voltage - JTAG programming at 3.3V will fail. (2) Assuming the N suffix is identical electrically - EPM7160SLC84-10N is RoHS lead-free; verify reflow profile matches 260C peak. (3) Over-driving 5V I/O into 3.3V peripherals - use series resistors or level translators. (4) Exceeding the 64-I/O pinout when planning the design - count GND/VCC/JTAG pins first to avoid running out of user I/Os.
The 10 ns tPD and 100 MHz fMAX make the EPM7160SLC84-10 suitable for high-speed glue logic, but signal-integrity issues can arise on long PCB traces. Keep output traces shorter than 50 mm when driving >50 pF loads; consider series damping resistors (22-33 ohm) on clock outputs to reduce ringing. Use controlled-impedance routing for signals faster than 50 MHz edges.
Compliance Information
Base part EPM7160SLC84-10 is SnPb (non-lead-free); the N suffix variant is lead-free. RoHS/REACH status not explicitly stated in verified data. AEC-Q100 not applicable for commercial-grade CPLD.
