EPM7160SQC160-10N vs EPM7160SQC160-6 Comparison
Detailed side-by-side comparison of EPM7160SQC160-10N by Intel and EPM7160SQC160-6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7160SQC160-10N
EPM7160SQC160-10N - 160 Macrocells MAX 7000S CPLD, 10ns, PQFP-160
EPM7160SQC160-10N NrndAltera
EPM7160SQC160-6
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 ObsoleteSpecification Comparison
| Parameter | EPM7160SQC160-10N | EPM7160SQC160-6 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.10 | $5.45 |
| Family | MAX 7000S | β |
| Macro Cells | 160 | β |
| Usable Gates | 3,200 | β |
| Logic Elements / Blocks | 10 Logic Array Blocks (LABs) | β |
| User I/O Pins | 104 | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 167 MHz | 167 MHz |
| Counter Speed (fCNT) | 100 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V (nominal 5 V) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| Operating Temperature | 0 C to 70 C (Commercial) | 0 C to 70 C (commercial) |
| Package | PQFP-160 (SQC) 31.2 x 31.2 mm | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-Compliant (Pb-bearing PQFP) | β |
| Memory Technology | EEPROM | β |
| Series | β | MAX 7000S |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Programmable Type | β | In System Programmable (ISP), EEPROM-based |
| Number of Macrocells | β | 160 |
| Number of Logic Elements/Blocks | β | 10 LABs (Logic Array Blocks) |
| Number of Usable Gates | β | 3,200 |
| Number of I/O Pins | β | 104 |
| Propagation Delay (tpd) | β | 6 ns (max, pin-to-pin) |
| Logic Family | β | CMOS, TTL-compatible I/O |
| Program/Erase Endurance | β | 100 cycles (EEPROM) |
| JTAG / Boundary Scan | β | IEEE Std 1149.1 compliant |
| Dedicated Input Pins | β | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) |