EPM7160SQC160-10N vs EPM7160SQC160-6 비교

다음의 상세 나란히 비교: EPM7160SQC160-10N 제조: Intel 및 EPM7160SQC160-6 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM7160SQC160-10N EPM7160SQC160-6
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND Obsolete
재고 상태 In Stock In Stock
단가 (USD) $8.10 $5.45
Family MAX 7000S —
Macro Cells 160 —
Usable Gates 3,200 —
Logic Elements / Blocks 10 Logic Array Blocks (LABs) —
User I/O Pins 104 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Internal Frequency 167 MHz 167 MHz
Counter Speed (fCNT) 100 MHz —
Supply Voltage (VCCINT) 5.0 V 4.75 V to 5.25 V (nominal 5 V)
In-System Programmability Yes (JTAG IEEE 1149.1) —
동작 온도 0 C to 70 C (Commercial) 0 C to 70 C (commercial)
패키지 PQFP-160 (SQC) 31.2 x 31.2 mm 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body
실장 유형 Surface Mount Surface Mount
RoHS 상태 Non-Compliant (Pb-bearing PQFP) —
Memory Technology EEPROM —
Series — MAX 7000S
Product Type — CPLD (Complex Programmable Logic Device)
Programmable Type — In System Programmable (ISP), EEPROM-based
Number of Macrocells — 160
Number of Logic Elements/Blocks — 10 LABs (Logic Array Blocks)
Number of Usable Gates — 3,200
Number of I/O Pins — 104
Propagation Delay (tpd) — 6 ns (max, pin-to-pin)
Logic Family — CMOS, TTL-compatible I/O
Program/Erase Endurance — 100 cycles (EEPROM)
JTAG / Boundary Scan — IEEE Std 1149.1 compliant
Dedicated Input Pins — 4 (GCLK1, GCLRn, OE1, OE2/GCLK2)

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청