EPM7160SQC160-6 vs EPM7160SQC160-10 Comparison

Detailed side-by-side comparison of EPM7160SQC160-6 by Altera and EPM7160SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7160SQC160-6 EPM7160SQC160-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.45 $12.20
Series MAX 7000S β€”
Product Type CPLD (Complex Programmable Logic Device) β€”
Programmable Type In System Programmable (ISP), EEPROM-based β€”
Number of Macrocells 160 β€”
Number of Logic Elements/Blocks 10 LABs (Logic Array Blocks) β€”
Number of Usable Gates 3,200 β€”
Number of I/O Pins 104 β€”
Propagation Delay (tpd) 6 ns (max, pin-to-pin) β€”
Maximum Internal Frequency 167 MHz β€”
Supply Voltage (VCCINT) 4.75 V to 5.25 V (nominal 5 V) 5.0 V
Logic Family CMOS, TTL-compatible I/O CMOS
Operating Temperature 0 C to 70 C (commercial) 0 C to +70 C (commercial)
Program/Erase Endurance 100 cycles (EEPROM) β€”
JTAG / Boundary Scan IEEE Std 1149.1 compliant β€”
Package 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body PQFP-160 (SQC160)
Mounting Type Surface Mount Surface Mount
Dedicated Input Pins 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) β€”
Family β€” MAX 7000S
Macro Cells β€” 160
Logic Elements / Gates β€” 3,200 usable gates
User I/Os β€” 104
Logic Array Blocks (LABs) β€” 10
Maximum Operating Frequency β€” 100 MHz
Pin-to-Pin Propagation Delay (tPD) β€” 10 ns
I/O Voltage Tolerance β€” 5.0 V
Programming Technology β€” EEPROM, in-system programmable
JTAG Support β€” IEEE 1149.1 (boundary-scan + ISP)
Process Technology β€” CMOS, EEPROM-based
RoHS Status β€” unknown
Lead-Free β€” unknown

Datasheets & Resources

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