EPM7160SQC160-6 vs EPM7160SQC160-10 Comparaison
Comparaison détaillée côte à côte de EPM7160SQC160-6 par Altera et EPM7160SQC160-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 ObsoleteAltera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteComparaison des spécifications
| Paramètre | EPM7160SQC160-6 | EPM7160SQC160-10 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,45 | $12,20 |
| Series | MAX 7000S | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | In System Programmable (ISP), EEPROM-based | — |
| Number of Macrocells | 160 | — |
| Number of Logic Elements/Blocks | 10 LABs (Logic Array Blocks) | — |
| Number of Usable Gates | 3,200 | — |
| Number of I/O Pins | 104 | — |
| Propagation Delay (tpd) | 6 ns (max, pin-to-pin) | — |
| Maximum Internal Frequency | 167 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (nominal 5 V) | 5.0 V |
| Logic Family | CMOS, TTL-compatible I/O | CMOS |
| Température de fonctionnement | 0 C to 70 C (commercial) | 0 C to +70 C (commercial) |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| JTAG / Boundary Scan | IEEE Std 1149.1 compliant | — |
| Boîtier | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body | PQFP-160 (SQC160) |
| Type de montage | Surface Mount | Surface Mount |
| Dedicated Input Pins | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) | — |
| Family | — | MAX 7000S |
| Macro Cells | — | 160 |
| Logic Elements / Gates | — | 3,200 usable gates |
| User I/Os | — | 104 |
| Logic Array Blocks (LABs) | — | 10 |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| I/O Voltage Tolerance | — | 5.0 V |
| Programming Technology | — | EEPROM, in-system programmable |
| JTAG Support | — | IEEE 1149.1 (boundary-scan + ISP) |
| Process Technology | — | CMOS, EEPROM-based |
| Statut RoHS | — | unknown |
| Lead-Free | — | unknown |