EPM7192EQC160-20 vs EPM7192EGM160-15 Comparison

Detailed side-by-side comparison of EPM7192EQC160-20 by Intel and EPM7192EGM160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7192EQC160-20 EPM7192EGM160-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Series MAX 7000 —
Programmable Type EE PLD (EEPROM-based) —
Number of Macrocells 192 —
Number of Logic Array Blocks 4 —
Number of User I/O Pins 124 (per package), 36 (per data source variant description) —
Delay Time (tPD) 20 ns —
Internal Counter Frequency (fCNT) 100 MHz typical —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
Operating Temperature -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
Package / Case 160-BQFP / 160-PQFP (28x28 mm) —
Mounting Type Surface Mount Through-hole (PGA socket)
In-System Programmable (ISP) Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) —
Programmable Security Bit Yes —
Power-Saving Mode Yes, programmable per macrocell —
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status [DATA_NEEDED: RoHS status - non-RoHS era part] [DATA_NEEDED: RoHS status]
Family — MAX 7000
Sub-family — MAX 7000E
Device — EPM7192E
Macrocells — 192
Usable Gates — 3750
Logic Array Blocks (LABs) — 12 (16 macrocells each)
User I/O Pins — 124
Package — 160-pin PGA (Pin Grid Array), ceramic
Pin-to-Pin Logic Delay (tPD) — 15 ns
Supply Voltage (Core) — 5 V ±5%
I/O Voltage — 3.3 V or 5 V configurable
Technology — CMOS EEPROM (0.5 µm)
Programming Interface — JTAG (ByteBlaster / BitBlaster)

Datasheets & Resources

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