EPM7192EQC160-20 vs EPM7192EGM160-15 比較
詳細並排比較 EPM7192EQC160-20 由 Intel 與 EPM7192EGM160-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 Obsolete規格比較
| 參數 | EPM7192EQC160-20 | EPM7192EGM160-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Series | MAX 7000 | — |
| Programmable Type | EE PLD (EEPROM-based) | — |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of User I/O Pins | 124 (per package), 36 (per data source variant description) | — |
| Delay Time (tPD) | 20 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz typical | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 封裝 / 外殼 | 160-BQFP / 160-PQFP (28x28 mm) | — |
| 安裝類型 | Surface Mount | Through-hole (PGA socket) |
| In-System Programmable (ISP) | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) | — |
| Programmable Security Bit | Yes | — |
| Power-Saving Mode | Yes, programmable per macrocell | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - non-RoHS era part] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 7000 |
| Sub-family | — | MAX 7000E |
| Device | — | EPM7192E |
| Macrocells | — | 192 |
| Usable Gates | — | 3750 |
| Logic Array Blocks (LABs) | — | 12 (16 macrocells each) |
| User I/O Pins | — | 124 |
| 封裝 | — | 160-pin PGA (Pin Grid Array), ceramic |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Supply Voltage (Core) | — | 5 V ±5% |
| I/O Voltage | — | 3.3 V or 5 V configurable |
| Technology | — | CMOS EEPROM (0.5 µm) |
| Programming Interface | — | JTAG (ByteBlaster / BitBlaster) |