EPM7192EQC160-20 vs EPM7192EGM160-20 Comparison
Detailed side-by-side comparison of EPM7192EQC160-20 by Intel and EPM7192EGM160-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteAltera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EQC160-20 | EPM7192EGM160-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $58.26 | $15.60 |
| Series | MAX 7000 | β |
| Programmable Type | EE PLD (EEPROM-based) | β |
| Number of Macrocells | 192 | β |
| Number of Logic Array Blocks | 4 | β |
| Number of User I/O Pins | 124 (per package), 36 (per data source variant description) | β |
| Delay Time (tPD) | 20 ns | β |
| Internal Counter Frequency (fCNT) | 100 MHz typical | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +125C (industrial) |
| Package / Case | 160-BQFP / 160-PQFP (28x28 mm) | β |
| Mounting Type | Surface Mount | β |
| In-System Programmable (ISP) | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) | β |
| Programmable Security Bit | Yes | β |
| Power-Saving Mode | Yes, programmable per macrocell | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| RoHS Status | [DATA_NEEDED: RoHS status - non-RoHS era part] | [DATA_NEEDED: RoHS status] |
| Family | β | MAX 7000 |
| Device Type | β | EE CMOS CPLD (Electrically Erasable) |
| Macrocells | β | 192 |
| Logic Array Blocks (LABs) | β | 12 |
| Usable Gates | β | 600 to 5,000 |
| Maximum User I/O Pins | β | 120 |
| Package | β | PGA-160 (160-pin Pin Grid Array) |
| Speed Grade | β | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | β | 20 ns |
| Counter Frequency (max) | β | 175.4 MHz |
| I/O Standards | β | 3.3 V or 5 V configurable |
| Global Clock Inputs | β | 2 (GCLK1, GCLK2) |
| In-System Programming | β | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | β | 100 cycles (EEPROM) |
| Technology Node | β | CMOS, second-generation MAX architecture |