EPM7192EQC160-20 vs EPM7192EGM160-20 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7192EQC160-20 disebabkan oleh Intel dan EPM7192EGM160-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteAltera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoletePengandingan Spesifikasi
| Parametr | EPM7192EQC160-20 | EPM7192EGM160-20 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Series | MAX 7000 | — |
| Programmable Type | EE PLD (EEPROM-based) | — |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of User I/O Pins | 124 (per package), 36 (per data source variant description) | — |
| Delay Time (tPD) | 20 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz typical | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Suhu Operasi | -40C to +85C (industrial) | -40C to +125C (industrial) |
| Kemasan / Case | 160-BQFP / 160-PQFP (28x28 mm) | — |
| Jenis Pemasangan | Surface Mount | — |
| In-System Programmable (ISP) | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) | — |
| Programmable Security Bit | Yes | — |
| Power-Saving Mode | Yes, programmable per macrocell | — |
| Aras MSL | [DATA_NEEDED: MSL rating] | — |
| Status RoHS | [DATA_NEEDED: RoHS status - non-RoHS era part] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 7000 |
| Device Type | — | EE CMOS CPLD (Electrically Erasable) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 600 to 5,000 |
| Maximum User I/O Pins | — | 120 |
| Kemasan | — | PGA-160 (160-pin Pin Grid Array) |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Counter Frequency (max) | — | 175.4 MHz |
| I/O Standards | — | 3.3 V or 5 V configurable |
| Global Clock Inputs | — | 2 (GCLK1, GCLK2) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| Technology Node | — | CMOS, second-generation MAX architecture |