EPM7192EQC160-20 vs EPM7192EGM160-20 对比

详细并排对比 EPM7192EQC160-20 出自 Intel 和 EPM7192EGM160-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7192EQC160-20 EPM7192EGM160-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $58.26 $15.60
Series MAX 7000 —
Programmable Type EE PLD (EEPROM-based) —
Number of Macrocells 192 —
Number of Logic Array Blocks 4 —
Number of User I/O Pins 124 (per package), 36 (per data source variant description) —
Delay Time (tPD) 20 ns —
Internal Counter Frequency (fCNT) 100 MHz typical —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
工作温度 -40C to +85C (industrial) -40C to +125C (industrial)
封装 / 外壳 160-BQFP / 160-PQFP (28x28 mm) —
安装类型 Surface Mount —
In-System Programmable (ISP) Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) —
Programmable Security Bit Yes —
Power-Saving Mode Yes, programmable per macrocell —
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS status - non-RoHS era part] [DATA_NEEDED: RoHS status]
Family — MAX 7000
Device Type — EE CMOS CPLD (Electrically Erasable)
Macrocells — 192
Logic Array Blocks (LABs) — 12
Usable Gates — 600 to 5,000
Maximum User I/O Pins — 120
封装 — PGA-160 (160-pin Pin Grid Array)
Speed Grade — -20 (20 ns pin-to-pin)
Pin-to-Pin Propagation Delay — 20 ns
Counter Frequency (max) — 175.4 MHz
I/O Standards — 3.3 V or 5 V configurable
Global Clock Inputs — 2 (GCLK1, GCLK2)
In-System Programming — Yes (JTAG IEEE 1149.1)
Program/Erase Endurance — 100 cycles (EEPROM)
Technology Node — CMOS, second-generation MAX architecture

数据手册与资源

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