EPM7192SQC160-7N vs EPM7192SQC160-10 Comparison
Detailed side-by-side comparison of EPM7192SQC160-7N by Altera and EPM7192SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N ObsoleteAltera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndSpecification Comparison
| Parameter | EPM7192SQC160-7N | EPM7192SQC160-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.60 | $18.25 |
| Family | MAX 7000S | MAX 7000S |
| Logic Family | CMOS | β |
| Macro Cells | 192 | β |
| Usable Gates | 3,750 | 3750 |
| User I/Os | 124 | 124 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Internal Counter Frequency | 167 MHz | β |
| Pin Count | 160 | β |
| Package Type | PQFP (Plastic Quad Flat Pack) | β |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Voltage (VCCIO) | 3.3 V / 5.0 V selectable | β |
| Programmability | EEPROM, In-System (JTAG ISP) | β |
| JTAG Support | IEEE 1149.1 Boundary Scan | β |
| Operating Temperature | 0 C to 70 C (Commercial) | β |
| Mounting Type | Surface Mount | β |
| Lead-Free (Pb-Free) | Yes (N suffix) | β |
| RoHS Status | Compliant (Pb-free terminal finish) | [DATA_NEEDED: RoHS status] |
| Macrocells | β | 192 |
| Logic Array Blocks (LABs) | β | 4 |
| Maximum Operating Frequency | β | 100 MHz |
| Program Memory Type | β | EEPROM |
| In-System Programmability | β | Yes (JTAG IEEE 1149.1) |
| Package | β | PQFP-160 (SQC) 28x28 mm |
| Pin/Package Type | β | Surface Mount, Gull-Wing |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Lead Finish | β | [DATA_NEEDED: lead finish] |