EPM7192SQC160-7N vs EPM7192SQC160-10 Comparación
Comparación detallada lado a lado de EPM7192SQC160-7N por Altera y EPM7192SQC160-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N ObsoleteAltera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndComparación de especificaciones
| Parámetro | EPM7192SQC160-7N | EPM7192SQC160-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,60 | $18,25 |
| Family | MAX 7000S | MAX 7000S |
| Logic Family | CMOS | — |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | 3750 |
| User I/Os | 124 | 124 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Internal Counter Frequency | 167 MHz | — |
| Recuento de pines | 160 | — |
| Package Type | PQFP (Plastic Quad Flat Pack) | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Voltage (VCCIO) | 3.3 V / 5.0 V selectable | — |
| Programmability | EEPROM, In-System (JTAG ISP) | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Temperatura de funcionamiento | 0 C to 70 C (Commercial) | — |
| Tipo de montaje | Surface Mount | — |
| Lead-Free (Pb-Free) | Yes (N suffix) | — |
| Estado RoHS | Compliant (Pb-free terminal finish) | [DATA_NEEDED: RoHS status] |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 100 MHz |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Encapsulado | — | PQFP-160 (SQC) 28x28 mm |
| Pin/Package Type | — | Surface Mount, Gull-Wing |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Lead Finish | — | [DATA_NEEDED: lead finish] |