EPM7192SQC160-7N vs EPM7192SQC160-15 Comparison

Detailed side-by-side comparison of EPM7192SQC160-7N by Altera and EPM7192SQC160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7192SQC160-7N

EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera

EPM7192SQC160-7N Obsolete
Altera
EPM7192SQC160-15

EPM7192SQC160-15 - MAX 7000S CPLD, 192 Macrocells, 15ns | Altera

EPM7192SQC160-15 Nrnd

Specification Comparison

Parameter EPM7192SQC160-7N EPM7192SQC160-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.60 $8.75
Family MAX 7000S MAX 7000S
Logic Family CMOS β€”
Macro Cells 192 β€”
Usable Gates 3,750 β€”
User I/Os 124 β€”
Propagation Delay (tPD) 7.5 ns β€”
Internal Counter Frequency 167 MHz β€”
Pin Count 160 β€”
Package Type PQFP (Plastic Quad Flat Pack) β€”
Supply Voltage (VCCINT) 5.0 V β€”
I/O Voltage (VCCIO) 3.3 V / 5.0 V selectable β€”
Programmability EEPROM, In-System (JTAG ISP) In-System (ISP) via JTAG IEEE Std 1149.1
JTAG Support IEEE 1149.1 Boundary Scan β€”
Operating Temperature 0 C to 70 C (Commercial) β€”
Mounting Type Surface Mount Surface Mount
Lead-Free (Pb-Free) Yes (N suffix) β€”
RoHS Status Compliant (Pb-free terminal finish) β€”
Device Type β€” CPLD - Complex Programmable Logic Device
Number of Macrocells β€” 192
Number of Logic Array Blocks β€” 4
Number of Usable Gates β€” 3750
User I/O Pins β€” 124
Pin-to-Pin Logic Delay (tPD) β€” 15 ns
Maximum Operating Frequency β€” 76.9 MHz
Supply Voltage β€” 5.0 V
Configuration Memory β€” EEPROM, non-volatile
Package β€” PQFP-160
Operating Temperature Range β€” [DATA_NEEDED: operating temperature range]
Process Technology β€” CMOS, EEPROM-based

Datasheets & Resources

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