EPM7192SQC160-7N vs EPM7192SQC160-15 Vergleich
Detaillierter Direktvergleich von EPM7192SQC160-7N von Altera und EPM7192SQC160-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N Obsolete
Spezifikationsvergleich
| Parameter | EPM7192SQC160-7N | EPM7192SQC160-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,60 | $8,75 |
| Family | MAX 7000S | MAX 7000S |
| Logic Family | CMOS | — |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | — |
| User I/Os | 124 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Internal Counter Frequency | 167 MHz | — |
| Pin-Anzahl | 160 | — |
| Package Type | PQFP (Plastic Quad Flat Pack) | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage (VCCIO) | 3.3 V / 5.0 V selectable | — |
| Programmability | EEPROM, In-System (JTAG ISP) | In-System (ISP) via JTAG IEEE Std 1149.1 |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Betriebstemperatur | 0 C to 70 C (Commercial) | — |
| Montageart | Surface Mount | Surface Mount |
| Lead-Free (Pb-Free) | Yes (N suffix) | — |
| RoHS-Status | Compliant (Pb-free terminal finish) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Versorgungsspannung | — | 5.0 V |
| Configuration Memory | — | EEPROM, non-volatile |
| Gehäuse | — | PQFP-160 |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Process Technology | — | CMOS, EEPROM-based |