EPM7192SQC160-7N vs EPM7192SQC160-15 比較
詳細並排比較 EPM7192SQC160-7N 由 Altera 與 EPM7192SQC160-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N Obsolete
規格比較
| 參數 | EPM7192SQC160-7N | EPM7192SQC160-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Logic Family | CMOS | — |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | — |
| User I/Os | 124 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Internal Counter Frequency | 167 MHz | — |
| 腳位數 | 160 | — |
| Package Type | PQFP (Plastic Quad Flat Pack) | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage (VCCIO) | 3.3 V / 5.0 V selectable | — |
| Programmability | EEPROM, In-System (JTAG ISP) | In-System (ISP) via JTAG IEEE Std 1149.1 |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| 工作溫度 | 0 C to 70 C (Commercial) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Lead-Free (Pb-Free) | Yes (N suffix) | — |
| RoHS 狀態 | Compliant (Pb-free terminal finish) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| 供應電壓 | — | 5.0 V |
| Configuration Memory | — | EEPROM, non-volatile |
| 封裝 | — | PQFP-160 |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Process Technology | — | CMOS, EEPROM-based |