EPM7192SQC160-7N vs EPM7192SQI160-10N Comparison

Detailed side-by-side comparison of EPM7192SQC160-7N by Altera and EPM7192SQI160-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7192SQC160-7N EPM7192SQI160-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.60 $35.90
Family MAX 7000S MAX 7000
Logic Family CMOS CMOS
Macro Cells 192 β€”
Usable Gates 3,750 3.75K (typical)
User I/Os 124 124
Propagation Delay (tPD) 7.5 ns β€”
Internal Counter Frequency 167 MHz β€”
Pin Count 160 160
Package Type PQFP (Plastic Quad Flat Pack) β€”
Supply Voltage (VCCINT) 5.0 V 5.0 V
I/O Voltage (VCCIO) 3.3 V / 5.0 V selectable β€”
Programmability EEPROM, In-System (JTAG ISP) β€”
JTAG Support IEEE 1149.1 Boundary Scan β€”
Operating Temperature 0 C to 70 C (Commercial) 0C to +70C (industrial, 'N' suffix)
Mounting Type Surface Mount Surface Mount
Lead-Free (Pb-Free) Yes (N suffix) β€”
RoHS Status Compliant (Pb-free terminal finish) Compliant (per lead-free PQFP package marking)
Series β€” MAX 7000S
Architecture β€” Second-generation MAX (CMOS, EEPROM)
Logic Elements / Macrocells β€” 192 macrocells
Package β€” PQFP-160 (QFP-160, plastic)
Pin-to-Pin Delay (tPD) β€” 10 ns
Maximum Internal Frequency β€” 167 MHz
Supply Voltage (VCCIO) β€” 5.0 V
In-System Programmability β€” Yes (5V ISP, JTAG)
Boundary-Scan Support β€” IEEE 1149.1 (JTAG)
Technology β€” 5V CMOS, EEPROM configuration memory
Propagation Delay β€” 7.5 ns to 10 ns (speed grade dependent)

Datasheets & Resources

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