EPM7256AETC100-10N vs EPM7256AEQC208-5N Comparison

Detailed side-by-side comparison of EPM7256AETC100-10N by Altera and EPM7256AEQC208-5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7256AETC100-10N EPM7256AEQC208-5N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 7000A MAX 7000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Usable Gates 5,000 5,000
Maximum User I/Os 84 —
Logic Elements / LABs 16 Logic Array Blocks —
Pin-to-Pin Logic Delay 10 ns —
Maximum Operating Frequency 125 MHz —
Supply Voltage (Core) 3.3 V —
MultiVolt I/O Support 2.5 V / 3.3 V / 5.0 V —
Programmability EEPROM, in-system via JTAG (IEEE 1149.1) —
Package 100-pin TQFP 208-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] —
Process Technology 0.30 µm EEPROM —
Dedicated Inputs 4 (global clock / clear / OE) 16
RoHS Status [DATA_NEEDED: not confirmed in provided data] unknown
Lead-Free / Pb-Free [DATA_NEEDED: not confirmed in provided data] —
Logic Family / Base Technology — CMOS, EEPROM-based
Macrocells — 256
User I/Os — 164
Number of Pins — 208
Supply Voltage (VCCINT) — 3.3 V
Maximum Internal Frequency — 172.4 MHz
Pin-to-Pin Propagation Delay (tPD) — 5.5 ns
Speed Grade — -5
Operating Temperature — 0 C to +70 C (Commercial)
Programming Interface — JTAG (IEEE Std. 1149.1) / ISP
MSL Level — [DATA_NEEDED: MSL Level]

Datasheets & Resources

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