EPM7256SQC208-15 vs EPM7256SQC208-15N Comparison
Detailed side-by-side comparison of EPM7256SQC208-15 by Altera and EPM7256SQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256SQC208-15 | EPM7256SQC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.65 | $0.00 |
| Family | MAX 7000S | β |
| Series | EPM7256 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | β |
| Usable Gates | 5000 | β |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Operating Temperature Range | 0 C to +70 C (Commercial) | β |
| Package | 208-pin PQFP (28x28 mm) | 208-pin PQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | β |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | β |
| In-System Programmability (ISP) | Yes | β |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| RoHS Status | Contains lead / RoHS non-compliant (per third-party listing) | Lead free / RoHS Compliant |
| Lead-Free Status | Contains lead | β |
| Pin-to-Pin Delay | β | 15 ns (speed grade -15) |
| Supply Voltage | β | 5 V |
| JTAG Interface | β | IEEE 1149.1 boundary-scan |
| In-System Programmability | β | Yes (ISP) |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | β | 16 macrocells per LAB |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Speed Grade | β | -15 |
| Product Category | β | CPLD - Complex Programmable Logic Devices |
| Manufacturer | β | Altera (Intel Programmable Solutions Group) |