EPM7256SQC208-15 vs EPM7256SQC208-15N Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-15 von Altera und EPM7256SQC208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-15 | EPM7256SQC208-15N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,65 | $0,00 |
| Family | MAX 7000S | — |
| Series | EPM7256 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Betriebstemperaturbereich | 0 C to +70 C (Commercial) | — |
| Gehäuse | 208-pin PQFP (28x28 mm) | 208-pin PQFP |
| Montageart | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| RoHS-Status | Contains lead / RoHS non-compliant (per third-party listing) | Lead free / RoHS Compliant |
| Lead-Free Status | Contains lead | — |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| Versorgungsspannung | — | 5 V |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| In-System Programmability | — | Yes (ISP) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |