EPM7256SQC208-15 vs EPM7256SQC208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SQC208-15 sa pamamagitan ng Altera at EPM7256SQC208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256SQC208-15 | EPM7256SQC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000S | — |
| Series | EPM7256 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Hanay ng Temperature na Operasyon | 0 C to +70 C (Commercial) | — |
| Packhaging | 208-pin PQFP (28x28 mm) | 208-pin PQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Tindminan RoHS | Contains lead / RoHS non-compliant (per third-party listing) | Lead free / RoHS Compliant |
| Lead-Free Status | Contains lead | — |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| Volte ng Pagbibigay | — | 5 V |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| In-System Programmability | — | Yes (ISP) |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |