EPM7256SQC208-15N vs EPM7256SRC208-15N Comparison
Detailed side-by-side comparison of EPM7256SQC208-15N by Altera and EPM7256SRC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7256SQC208-15N
EPM7256SQC208-15N - MAX 7000S CPLD 256 Macrocell | Altera
EPM7256SQC208-15N ObsoleteAltera
EPM7256SRC208-15N
EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera
EPM7256SRC208-15N ObsoleteSpecification Comparison
| Parameter | EPM7256SQC208-15N | EPM7256SRC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $27.20 |
| Series | MAX 7000S | MAX 7000S |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | β |
| Supply Voltage | 5 V | 5 V |
| Package | 208-pin PQFP | 208-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG Interface | IEEE 1149.1 boundary-scan | β |
| In-System Programmability | Yes (ISP) | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS Status | Lead free / RoHS Compliant | Compliant (N suffix) |
| Logic Array Blocks | 16 macrocells per LAB | β |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| Speed Grade | -15 | β |
| Product Category | CPLD - Complex Programmable Logic Devices | β |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Usable Gates | β | 5,000 |
| Logic Array Blocks (LABs) | β | 16 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Counter Frequency | β | 76.9 MHz |
| I/O Standard | β | 5 V TTL/CMOS compatible |
| Lead Free | β | Yes (N suffix) |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Number of Terminals | β | 208 |