EPM7256SQC208-15N vs EPM7256SRC208-15N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SQC208-15N sa pamamagitan ng Altera at EPM7256SRC208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM7256SRC208-15N EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N Obsolete

Pagsanggunian na paghahambing

Parametro EPM7256SQC208-15N EPM7256SRC208-15N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series MAX 7000S MAX 7000S
Macrocells 256 256
User I/O Pins 164 164
Pin-to-Pin Delay 15 ns (speed grade -15) —
Volte ng Pagbibigay 5 V 5 V
Packhaging 208-pin PQFP 208-pin RQFP (PowerQuad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
JTAG Interface IEEE 1149.1 boundary-scan —
In-System Programmability Yes (ISP) Yes (IEEE 1149.1 JTAG)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Tindminan RoHS Lead free / RoHS Compliant Compliant (N suffix)
Logic Array Blocks 16 macrocells per LAB —
Interconnect Programmable Interconnect Array (PIA) —
Speed Grade -15 —
Product Category CPLD - Complex Programmable Logic Devices —
Manufacturer Altera (Intel Programmable Solutions Group) —
Usable Gates — 5,000
Logic Array Blocks (LABs) — 16
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Counter Frequency — 76.9 MHz
I/O Standard — 5 V TTL/CMOS compatible
Lead Free — Yes (N suffix)
Level ng MSL — [DATA_NEEDED: MSL level]
Number of Terminals — 208

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