EPM7256SQC208-15N vs EPM7256SRC208-15N 对比

详细并排对比 EPM7256SQC208-15N 出自 Altera 和 EPM7256SRC208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7256SRC208-15N EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N Obsolete

规格对比

参数 EPM7256SQC208-15N EPM7256SRC208-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $27.20
Series MAX 7000S MAX 7000S
Macrocells 256 256
User I/O Pins 164 164
Pin-to-Pin Delay 15 ns (speed grade -15) —
电源电压 5 V 5 V
封装 208-pin PQFP 208-pin RQFP (PowerQuad Flat Pack)
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
JTAG Interface IEEE 1149.1 boundary-scan —
In-System Programmability Yes (ISP) Yes (IEEE 1149.1 JTAG)
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS 状态 Lead free / RoHS Compliant Compliant (N suffix)
Logic Array Blocks 16 macrocells per LAB —
Interconnect Programmable Interconnect Array (PIA) —
Speed Grade -15 —
Product Category CPLD - Complex Programmable Logic Devices —
Manufacturer Altera (Intel Programmable Solutions Group) —
Usable Gates — 5,000
Logic Array Blocks (LABs) — 16
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Counter Frequency — 76.9 MHz
I/O Standard — 5 V TTL/CMOS compatible
Lead Free — Yes (N suffix)
MSL 等级 — [DATA_NEEDED: MSL level]
Number of Terminals — 208

数据手册与资源

浏览全部产品 创建 BOM 获取报价