EPM7256SQI208-10 vs EPM7256SQC208-7N Comparison

Detailed side-by-side comparison of EPM7256SQI208-10 by Altera and EPM7256SQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7256SQI208-10 EPM7256SQC208-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.40 $27.20
Device Family MAX 7000 (EPM7256) β€”
Macrocells 256 256
Usable Gates 5000 5,000
Logic Array Blocks 16 β€”
Maximum User I/O Pins 164 β€”
Propagation Delay (tPD) 10 ns β€”
Supply Voltage Range 4.5 V to 5.5 V β€”
Technology CMOS EEPROM CMOS EEPROM
Configuration Memory EEPROM (non-volatile) Non-volatile EEPROM (no external config needed)
In-System Programmable Yes (IEEE 1149.1 JTAG) β€”
Package 208-pin PQFP (QFP208) 208-pin PQFP (Plastic Quad Flat Pack)
Package Body Material Plastic/Epoxy β€”
Terminal Form Gull Wing β€”
Operating Temperature Range -40 C to +85 C (Industrial) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] Compliant (N suffix = lead-free)
JESD-30 Package Code S-PQFP-G208 β€”
JESD-609 Terminal Finish Code E3 β€”
Family β€” MAX 7000S
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 16
User I/O Pins β€” 164
Speed Grade β€” -7 (7.5 ns pin-to-pin)
Maximum Frequency β€” 128.2 MHz
Supply Voltage (VCC) β€” 5 V
Operating Temperature β€” Commercial (0C to +70C)
JTAG Interface β€” IEEE 1149.1 boundary-scan (ISP capable)
Minimum DC Input Voltage β€” -0.5 V
Input Undershoot Tolerance β€” -2.0 V for <100 mA, <20 ns
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Open-Drain Output β€” Optional per I/O pin

Datasheets & Resources

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