Altera

EPM7256SQI208-10 - MAX 7000 CPLD 256 Macrocell 10ns | Altera

MPN: EPM7256SQI208-10 ✗ End of Life
In Stock Ships in 1-3 business days
4.5 V to 5.5 V Vdss 208-pin PQFP (QFP208) Package EEPROM (non-volatile) Memory
From $0.4 USD / Unit
MOQ: 1 |
Price updated: 2026-09-12
Volume Pricing
Qty Unit Price Extended
1 $0.5 $0.50
10 $0.48 $4.80
100 $0.45 $45.00
500 $0.42 $210.00
1,000 $0.4 $400.00
ℹ️ All prices are in USD

Drop-in alternatives for EPM7256SQI208-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPM7256SQI208-10N

✅ Drop-In
📦 208-pin PQFP (QFP208)
lead-free (RoHS) terminal finish, otherwise identical 256 macrocell / 10 ns / industrial temp

📋 Reference alternative (not in catalog)

EPM7256SQC208-10

✅ Drop-In
Intel
📦 208-pin PQFP (QFP208)
MAX 7000S · CPLD (Complex Programmable Logic Device) · 256 · 16 · 5,000 · 164 · 10 ns · Up to 175.4 MHz

✓ In Stock

$11.2 / Unit

View Datasheet →

EPM7256SQC208-7

✅ Drop-In
Altera
📦 208-pin PQFP (QFP208)
MAX 7000S (EPM7256S) · 256 · 5,000 · 164 · 7.5 ns · 128.2 MHz · 5.0 V · EEPROM (non-volatile)

✓ In Stock

Contact for price

View Datasheet →

EPM7256SQC208-7N

✅ Drop-In
Altera
📦 208-pin PQFP (QFP208)
MAX 7000S · CPLD (Complex Programmable Logic Device) · 256 · 5,000 · 16 · 164 · -7 (7.5 ns pin-to-pin) · 128.2 MHz

✓ In Stock

$27.2 / Unit

View Datasheet →

EPM7256SQC208-15

✅ Drop-In
Altera
📦 208-pin PQFP (QFP208)
MAX 7000S · EPM7256 · CPLD (Complex Programmable Logic Device) · 256 · 16 · 5000 · 164 · 15 ns

✓ In Stock

$3.65 / Unit

View Datasheet →

EPM7256SQC208-15N

✅ Drop-In
Altera
📦 208-pin PQFP (QFP208)
MAX 7000S · 256 · 164 · 15 ns (speed grade -15) · 5 V · 208-pin PQFP · Surface Mount · EEPROM (non-volatile)

✓ In Stock

Contact for price

View Datasheet →

EPM7256SQI208-10 Maximum Ratings & Electrical Characteristics

Device Family MAX 7000 (EPM7256)
Macrocells 256
Usable Gates 5000
Logic Array Blocks 16
Maximum User I/O Pins 164
Propagation Delay (tPD) 10 ns
Supply Voltage Range 4.5 V to 5.5 V
Technology CMOS EEPROM
Configuration Memory EEPROM (non-volatile)
In-System Programmable Yes (IEEE 1149.1 JTAG)
Package 208-pin PQFP (QFP208)
Package Body Material Plastic/Epoxy
Terminal Form Gull Wing
Operating Temperature Range -40 C to +85 C (Industrial)
Mounting Type Surface Mount
JESD-30 Package Code S-PQFP-G208
JESD-609 Terminal Finish Code E3

EPM7256SQI208-10 Pin Configuration

QFP-208 Package Pinout Diagram QFP-208 28x28mm, P0.5mm, JEDEC. 1 52 QFP-208
Pin 1 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 2 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 3 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 4 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 5 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 6 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 7 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 8 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 9 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 10 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 11 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 12 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 13 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 14 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 15 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 16 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 17 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 18 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 19 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 20 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 21 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 22 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 23 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 24 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 25 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 26 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 27 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 28 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 29 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 30 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 31 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 32 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 33 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 34 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 35 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 36 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 37 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 38 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 39 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 40 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 41 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 42 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 43 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 44 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 45 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 46 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 47 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 48 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 49 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 50 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 51 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 52 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 53 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 54 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 55 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 56 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 57 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 58 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 59 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 60 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 61 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 62 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 63 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 64 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 65 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 66 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 67 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 68 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 69 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 70 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 71 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 72 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 73 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 74 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 75 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 76 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 77 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 78 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 79 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 80 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 81 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 82 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 83 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 84 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 85 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 86 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 87 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 88 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 89 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 90 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 91 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 92 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 93 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 94 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 95 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 96 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 97 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 98 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 99 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 100 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 101 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 102 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 103 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 104 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 105 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 106 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 107 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 108 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 109 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 110 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 111 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 112 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 113 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 114 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 115 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 116 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 117 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 118 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 119 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 120 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 121 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 122 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 123 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 124 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 125 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 126 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 127 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 128 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 129 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 130 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 131 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 132 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 133 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 134 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 135 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 136 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 137 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 138 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 139 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 140 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 141 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 142 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 143 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 144 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 145 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 146 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 147 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 148 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 149 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 150 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 151 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 152 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 153 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 154 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 155 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 156 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 157 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 158 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 159 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 160 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 161 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 162 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 163 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 164 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 165 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 166 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 167 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 168 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 169 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 170 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 171 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 172 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 173 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 174 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 175 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 176 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 177 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 178 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 179 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 180 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 181 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 182 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 183 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 184 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 185 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 186 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 187 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 188 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 189 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 190 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 191 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 192 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 193 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 194 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 195 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 196 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 197 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 198 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 199 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 200 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 201 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 202 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 203 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 204 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 205 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 206 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 207 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)
Pin 208 I/O — General-purpose user I/O (per MAX 7000 datasheet pin assignment)

Safe Operating Area (SOA) & Thermal Characteristics

Safe Operating Area Chart Default safe operating area chart for EPM7256SQI208-10 Drain-to-Source Voltage (Vds) Drain Current (Id)

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM7256SQI208-10 is suitable for 6 applications: Legacy 5 V Address Decoding and Chip-Select Logic, Industrial Control State Machines, Bus Interface and Glue Logic for Legacy Peripherals, Replacement of Discrete 74-Series Logic, Instrumentation and Test Equipment Control, Telecom and Networking Line-Card Glue Logic.

🏭

Legacy 5 V Address Decoding and Chip-Select Logic

The EPM7256SQI208-10 fits legacy 5 V microprocessor address decoding because its 4.5 V to 5.5 V supply range interfaces directly to 5 V TTL/CMOS buses without level shifters, and its 10 ns pin-to-pin delay keeps chip-select timing within a single processor bus cycle. With 256 macrocells and 164 user I/O, it can absorb the address comparators, wait-state generators, and chip-select decoders that would otherwise require a dozen 74-series packages. The EEPROM configuration is non-volatile, so the decode logic is live immediately at power-up with no configuration PROM. A typical implementation places the CPLD between the CPU address bus and peripheral chip-select pins, using the programmable interconnect array for deterministic routing. The trade-off versus a modern MAX V CPLD is higher static current and a larger 208-pin PQFP footprint, but no board redesign is needed for existing 5 V systems.

🏭

Industrial Control State Machines

The EPM7256SQI208-10 is well suited to industrial control state machines because its -40 C to +85 C industrial temperature rating covers factory-floor and outdoor cabinet environments, and its EEPROM configuration survives power interruptions without reloading. The 256 macrocells can implement multi-state sequencers, handshake controllers, and safety interlocks with deterministic 10 ns timing, which is critical when state transitions must complete within a fixed scan period. Designers typically clock the CPLD from the system controller and use the 164 I/O pins to drive relays, opto-isolators, and motor-driver enable lines. Unlike an SRAM FPGA, the MAX 7000 device has no configuration boot delay, so the machine returns to a known state immediately after power restoration. The main trade-off is the 5 V supply requirement, which may need a dedicated rail in modern 3.3 V control cabinets.

🌐

Bus Interface and Glue Logic for Legacy Peripherals

The EPM7256SQI208-10 serves as bus-interface glue logic when bridging legacy 5 V peripherals such as ISA-style controllers, UARTs, and parallel interfaces to a host processor. Its 5 V CMOS I/O drives TTL-level peripheral buses directly, and the 256 macrocells provide enough capacity to implement address latching, read/write strobe generation, and wait-state insertion in one device. The programmable interconnect array gives fixed, predictable propagation delays, so bus timing margins can be calculated from the 10 ns tPD rather than estimated from place-and-route reports. In-system programmability through IEEE 1149.1 JTAG allows field firmware updates of the glue logic without removing the board. The trade-off is that the 208-pin PQFP consumes more board area than a modern small-form-factor CPLD, but it preserves the existing 5 V bus topology.

🔧

Replacement of Discrete 74-Series Logic

The EPM7256SQI208-10 consolidates boards full of 74-series TTL logic into a single 208-pin CPLD, reducing component count, board area, and assembly cost. Its 256 macrocells and 5,000 usable gates can absorb counters, shift registers, multiplexers, and comparators that would otherwise occupy dozens of discrete packages. Because the MAX 7000 architecture is EEPROM-based, the replacement logic is non-volatile and needs no external configuration device, unlike an SRAM FPGA. The 5 V supply and TTL-compatible I/O thresholds match the electrical environment of the original 74-series design, so no level shifting is required. Engineers typically migrate one functional block at a time and verify timing against the original discrete implementation using the 10 ns tPD specification. The trade-off is that a CPLD redesign requires logic synthesis and JTAG programming infrastructure.

🔧

Instrumentation and Test Equipment Control

The EPM7256SQI208-10 is used in instrumentation and test equipment for front-panel control, trigger sequencing, and measurement timing because its deterministic 10 ns propagation delay allows repeatable trigger-to-output timing that SRAM FPGAs cannot guarantee without extensive timing closure. The industrial temperature rating supports benchtop and rack-mount instruments that operate outside a climate-controlled lab, and the EEPROM configuration ensures the instrument boots into a known logic state without a configuration load. The 164 user I/O pins can drive front-panel LEDs, read rotary encoders, and sequence analog multiplexers. Designers often pair the CPLD with precision analog front-ends and use the CPLD to generate conversion start pulses. The trade-off is the 5 V supply and the relatively high static power of the MAX 7000 process compared with modern low-power CPLDs.

🌐

Telecom and Networking Line-Card Glue Logic

The EPM7256SQI208-10 provides glue logic on legacy telecom and networking line cards, where 5 V logic and deterministic timing are still required for backplane interface control, clock multiplexing, and status register aggregation. The 256 macrocells can implement multiple independent state machines for per-channel control, while the 164 I/O pins interface to backplane connectors and status LEDs. The EEPROM configuration means the line card initializes its control logic immediately on power-up, which is important for cards that must be ready before the host processor completes its boot sequence. The 10 ns tPD supports backplane control timing at rates up to roughly 100 MHz for simple paths. The trade-off versus a modern CPLD is higher power and a larger package, but the part preserves existing 5 V backplane designs without a costly re-spin.

What is the EPM7256SQI208-10?
The EPM7256SQI208-10 is an Altera MAX 7000 series EEPROM-based CPLD with 256 macrocells, 5,000 usable gates, and a 10 ns pin-to-pin propagation delay, packaged in a 208-pin PQFP. It operates from a 5 V supply (4.5 V to 5.5 V) and is rated for the industrial temperature range of -40 C to +85 C, making it suitable for legacy 5 V glue-logic and address-decoding designs.
What is the propagation delay of the EPM7256SQI208-10?
The EPM7256SQI208-10 has a pin-to-pin propagation delay (tPD) of 10 ns, as indicated by the -10 speed grade suffix. This supports system clock rates up to approximately 100 MHz for simple logic paths. The MAX 7000 architecture uses a programmable interconnect array with deterministic timing, so the 10 ns delay is predictable and does not vary with placement like SRAM FPGA routing.
How many macrocells and I/O pins does the EPM7256SQI208-10 have?
The EPM7256SQI208-10 contains 256 macrocells organized into 16 logic array blocks, with up to 164 user I/O pins available in the 208-pin PQFP package. The 256 macrocells provide 5,000 usable gates for implementing combinational and sequential logic. Distributor data confirms the 256 macrocell count and 208 terminal count for this device.
What is the difference between EPM7256SQI208-10 and EPM7256SQC208-10?
The EPM7256SQI208-10 is the industrial temperature grade (-40 C to +85 C), while the EPM7256SQC208-10 is the commercial temperature grade (0 C to +70 C). Both share the same 256 macrocells, 10 ns speed grade, and 208-pin PQFP footprint, so they are pin-compatible. Choose the SQI version for industrial or outdoor equipment and the SQC version for cost-sensitive commercial designs.
What is the difference between EPM7256SQI208-10 and EPM7256SQI208-10N?
The EPM7256SQI208-10N is the lead-free (RoHS-compliant) version of the EPM7256SQI208-10, indicated by the N suffix. Both are industrial-grade 256-macrocell MAX 7000 CPLDs in the same 208-pin PQFP package with a 10 ns speed grade. For new production requiring RoHS compliance, select the -10N variant; the -10 variant may use leaded terminal finish.
What is the difference between EPM7256SQI208-10 and EPM7256SQC208-7?
The EPM7256SQC208-7 is a faster commercial-grade part with a 7 ns propagation delay, while the EPM7256SQI208-10 is an industrial-grade part with a 10 ns delay. The -7 speed grade supports higher clock rates but is only rated 0 C to +70 C. Choose the -10 industrial version when the design must operate below 0 C or above +70 C, and the -7 commercial version when maximum speed is the priority.
Is the EPM7256SQI208-10 still in production?
The EPM7256SQI208-10 is a legacy MAX 7000 family device and is classified as not recommended for new designs (NRND). Intel/Altera has migrated customers to MAX II and MAX V CPLDs. The part remains available through independent distributors and aftermarket channels, but engineers starting new designs should evaluate MAX II (EPM240/EPM570) or MAX V (5M series) for long-term supply.
Where can I buy the EPM7256SQI208-10?
The EPM7256SQI208-10 is available through independent distributors including Veswin Electronics, Microchip USA, FPGAkey, Jotrin Electronics, and NY-Components, as well as through Octopart's distributor comparison. Reference pricing from NY-Components is approximately $0.50 per unit as of 2026-09-13, though pricing varies significantly by quantity and channel. Always verify authenticity when purchasing legacy Altera parts from independent distributors.
What is the price of the EPM7256SQI208-10?
Reference pricing for the EPM7256SQI208-10 is approximately $0.50 per unit as of 2026-09-13, based on NY-Components listing data. Because this is a legacy NRND part, pricing from independent distributors can fluctuate widely with availability. For volume pricing, request quotes from multiple distributors and compare against the lead-free EPM7256SQI208-10N variant, which may have different stock levels.
What is the best drop-in replacement for the EPM7256SQI208-10?
The best drop-in replacement is the EPM7256SQI208-10N, which is the lead-free version of the same device with identical 256 macrocells, 10 ns speed grade, and 208-pin PQFP footprint. If the industrial temperature range is not required, the EPM7256SQC208-10 is pin-compatible with a commercial temperature rating. Both alternatives share the same package and pinout, so no PCB redesign is needed.
Can the EPM7256SQC208-10 replace the EPM7256SQI208-10?
Yes, the EPM7256SQC208-10 can replace the EPM7256SQI208-10 in applications that do not require the industrial temperature range. Both are 256-macrocell MAX 7000 CPLDs with a 10 ns speed grade in the same 208-pin PQFP package. The key difference is temperature rating: the SQC version is rated 0 C to +70 C, while the SQI version is rated -40 C to +85 C. Verify your thermal environment before substituting.
What is the best Altera equivalent for the EPM7256SQI208-10?
Within the Altera MAX 7000 family, the closest equivalents are the EPM7256SQC208-10 (commercial temperature, same speed) and the EPM7256SQI208-10N (lead-free, same temperature and speed). For a newer architecture, Altera's MAX II EPM570 or MAX V 5M240Z offer higher density and lower power but require a different package and pinout, so they are not drop-in replacements.
What are the key specifications of the EPM7256SQI208-10 that engineers should know?
The EPM7256SQI208-10 is a 5 V EEPROM CPLD with 256 macrocells, 5,000 usable gates, 164 maximum user I/O, and a 10 ns pin-to-pin delay in a 208-pin PQFP. It supports in-system programming via IEEE 1149.1 JTAG, operates from 4.5 V to 5.5 V, and is rated -40 C to +85 C. Its non-volatile EEPROM configuration retains logic after power-down without external configuration memory.
Where can I download the EPM7256SQI208-10 datasheet PDF?
The EPM7256SQI208-10 datasheet is available from the Intel/Altera MAX 7000 documentation page and from distributor datasheet mirrors such as EEWORLD Datasheet and FPGAkey. The MAX 7000 family datasheet covers the EPM7256 device, including pinout, timing, and programming specifications. Always download from the manufacturer or a reputable distributor to ensure you have the current revision.
What is the pinout of the EPM7256SQI208-10?
The EPM7256SQI208-10 uses a 208-pin Plastic Quad Flat Pack (PQFP) with gull-wing terminals and a square body, per the JESD-30 code S-PQFP-G208. The pinout includes dedicated VCC and GND pins, JTAG pins (TCK, TMS, TDI, TDO), and up to 164 user I/O pins. Consult the MAX 7000 family datasheet for the complete pin assignment table before designing the PCB footprint.
Is the EPM7256SQI208-10 RoHS compliant?
The EPM7256SQI208-10 base part number does not carry the N suffix, so its RoHS status is not confirmed by the available data and should be verified with the distributor. The EPM7256SQI208-10N is the explicitly lead-free, RoHS-compliant variant. For designs requiring RoHS compliance, specify the -10N version and request a compliance certificate from the supplier.

Engineering reference data for EPM7256SQI208-10 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM7256SQI208-10 when you need a 256-macrocell, 5 V MAX 7000 CPLD rated for the industrial temperature range of -40 C to +85 C, such as factory automation, outdoor instrumentation, or legacy 5 V systems that must operate outside a climate-controlled environment. Choose the EPM7256SQI208-10N if the same design must also be RoHS-compliant, since it is the lead-free version with an identical footprint and speed grade. Choose the EPM7256SQC208-10 if the application is confined to 0 C to +70 C and cost is the priority. Choose the EPM7256SQC208-7 only when a 7 ns propagation delay is required and the commercial temperature range is acceptable. For new designs, evaluate Altera MAX II or MAX V CPLDs, which offer lower power and smaller packages but require a board re-spin because they are not pin-compatible with the MAX 7000 family.

Comparison with Alternatives

Parameter This Product EPM7256SQI208-10N EPM7256SQC208-10 EPM7256SQC208-7 EPM7256SQC208-15
Package 208-pin PQFP (QFP208) 208-pin PQFP - same 208-pin PQFP - same 208-pin PQFP - same 208-pin PQFP - same
Brand Altera Altera Altera Altera Altera
Macrocells 256 256 256 256 256
Propagation Delay (tPD) 10 ns 10 ns 10 ns 7 ns 15 ns
Operating Temperature Range -40 C to +85 C (Industrial) -40 C to +85 C (Industrial) 0 C to +70 C (Commercial) 0 C to +70 C (Commercial) 0 C to +70 C (Commercial)
Supply Voltage Range 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V
RoHS / Lead-Free [DATA_NEEDED: RoHS status] Lead-free (N suffix) [DATA_NEEDED] [DATA_NEEDED] [DATA_NEEDED]
In-System Programmable (JTAG) Yes (IEEE 1149.1) Yes (IEEE 1149.1) Yes (IEEE 1149.1) Yes (IEEE 1149.1) Yes (IEEE 1149.1)
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile)
Maximum User I/O 164 164 164 164 164

Key Differentiators

  • Industrial temperature rating (vs EPM7256SQC208-10)
  • Lead-free option available in same footprint (vs EPM7256SQI208-10N)
  • Faster speed grade available for timing-critical paths (vs EPM7256SQC208-7)

Design Notes

Decouple every VCC pin of the EPM7256SQI208-10 with a 0.1 uF ceramic capacitor placed as close to the package pin as possible, and add at least one 10 uF bulk capacitor per power plane. The MAX 7000 family draws transient current during logic switching, and inadequate decoupling causes ground bounce that can corrupt the programmable interconnect array timing. Estimated: with 164 simultaneously switching outputs at 5 V, transient current can exceed several hundred milliamps for a few nanoseconds, so keep the decoupling loop inductance low by using short, wide traces to a solid ground plane.

Route the JTAG signals (TCK, TMS, TDI, TDO) as short, controlled-impedance traces and keep them away from high-speed clock nets to avoid programming failures. Provide a dedicated 10-pin or 14-pin JTAG header with a clean ground return. The 208-pin PQFP has a 0.5 mm lead pitch, so use a solder-mask-defined footprint and verify the pad geometry against the MAX 7000 datasheet land pattern before fabrication. Place the device so that all decoupling capacitors are on the same side of the board as the CPLD.

Do not assume the EPM7256SQI208-10 is a drop-in for newer MAX II or MAX V CPLDs - those families use different packages, supply voltages, and pinouts, so a board re-spin is required. Also verify the speed grade: the -10 suffix means 10 ns tPD, and substituting a -15 part reduces the maximum clock rate by roughly 33%. Estimated: a design that closes timing at 10 ns may fail at 15 ns, so re-run static timing analysis if a slower grade is used as a substitute.

Compliance Information

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Lead Free
Unknown
Halogen Free
Unknown
Conflict Minerals
Unknown

RoHS and lead-free status for the base EPM7256SQI208-10 part number is not confirmed by the available web data; the EPM7256SQI208-10N variant is the explicitly lead-free version. AEC-Q100 is not applicable to this commercial/industrial CPLD.

Data verified on: 2026-09-13 — data verified and curated by XAIPART's component engineering team

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Related Components & Terms

Altera Intel EPM7256SQI208-10 EPM7256SQI208-10N EPM7256SQC208-10 EPM7256SQC208-7 MAX 7000 CPLD Complex Programmable Logic Device EEPROM macrocell PQFP QFP208 IEEE 1149.1 JTAG 5 V CMOS propagation delay programmable interconnect array industrial temperature range RoHS address decoding glue logic in-system programmable
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