EPM7256SQI208-10 vs EPM7256SQC208-7N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7256SQI208-10 disebabkan oleh Altera dan EPM7256SQC208-7N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM7256SQI208-10 | EPM7256SQC208-7N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Device Family | MAX 7000 (EPM7256) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5000 | 5,000 |
| Logic Array Blocks | 16 | — |
| Maximum User I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Technology | CMOS EEPROM | CMOS EEPROM |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| In-System Programmable | Yes (IEEE 1149.1 JTAG) | — |
| Kemasan | 208-pin PQFP (QFP208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Package Body Material | Plastic/Epoxy | — |
| Terminal Form | Gull Wing | — |
| Gambaran Suhu Operasi | -40 C to +85 C (Industrial) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| JESD-30 Package Code | S-PQFP-G208 | — |
| JESD-609 Terminal Finish Code | E3 | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 164 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Suhu Operasi | — | Commercial (0C to +70C) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |