EPM7256SRC208-10N vs EPM7256SQC208-15N Comparison
Detailed side-by-side comparison of EPM7256SRC208-10N by Intel and EPM7256SQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256SRC208-10N | EPM7256SQC208-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000S | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 100 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Compliant (N suffix = lead-free) | Lead free / RoHS Compliant |
| Logic Levels | 5.0 V TTL/CMOS compatible | — |
| Number of Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Maximum User Flash Memory | [DATA_NEEDED: user flash memory] | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |