EPM7256SRC208-10N vs EPM7256SQC208-15N 比較
詳細な並列比較: EPM7256SRC208-10N メーカー: Intel および EPM7256SQC208-15N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SRC208-10N | EPM7256SQC208-15N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.20 | $0.00 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000S | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 100 MHz | — |
| 電源電圧 | 5.0 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| パッケージ | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS ステータス | Compliant (N suffix = lead-free) | Lead free / RoHS Compliant |
| Logic Levels | 5.0 V TTL/CMOS compatible | — |
| Number of Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Maximum User Flash Memory | [DATA_NEEDED: user flash memory] | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |