EPM7256SRC208-10N vs EPM7256SQC208-15N 对比
详细并排对比 EPM7256SRC208-10N 出自 Intel 和 EPM7256SQC208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256SRC208-10N | EPM7256SQC208-15N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.20 | $0.00 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000S | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 100 MHz | — |
| 电源电压 | 5.0 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| 封装 | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS 状态 | Compliant (N suffix = lead-free) | Lead free / RoHS Compliant |
| Logic Levels | 5.0 V TTL/CMOS compatible | — |
| Number of Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| Maximum User Flash Memory | [DATA_NEEDED: user flash memory] | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |