EPM7512BQC208-10 vs EPM7512BQC208-5 Comparison
Detailed side-by-side comparison of EPM7512BQC208-10 by Altera and EPM7512BQC208-5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7512BQC208-10 - 512-Macrocell MAX 7000B CPLD, 10ns, PQFP-208 | Altera (Intel)
EPM7512BQC208-10 NrndSpecification Comparison
| Parameter | EPM7512BQC208-10 | EPM7512BQC208-5 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000B | MAX 7000B |
| Series | MAX 7000B | — |
| Macrocells | 512 | 512 |
| Logic Elements / Blocks | 32 LABs (16 macrocells per LAB) | — |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 176 | — |
| Propagation Delay (tpd) | 10 ns (max, pin-to-pin) | — |
| Programmable Type | In-System Programmable (EEPROM) | In System Programmable (ISP) |
| Internal Supply Voltage | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to 70C (commercial) |
| Package / Case | 208-pin PQFP (28x28 mm), S-PQFP-G208 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | CMOS, Multiple Array Matrix (MAX) second-generation | — |
| JTAG / Boundary Scan | IEEE Std 1149.1 compliant | — |
| MSL Level | [DATA_NEEDED: MSL Level] | — |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 176 |
| Logic Array Blocks | — | 16 |
| Propagation Delay (tPD) | — | 5 ns |
| Internal Frequency | — | 163.9 MHz |
| Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V (2.5 V nominal) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Package | — | 208-pin PQFP (28x28 mm) |
| Package Code | — | FQFP / S-PQFP-G208 |
| Terminal Pitch | — | 0.5 mm |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Speed Grade | — | -5 (fastest MAX 7000B grade) |