EPM7512BQC208-7 vs EPM7512BQC208-10 Comparison
Detailed side-by-side comparison of EPM7512BQC208-7 by Altera and EPM7512BQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7512BQC208-10 - 512-Macrocell MAX 7000B CPLD, 10ns, PQFP-208 | Altera (Intel)
EPM7512BQC208-10 NrndSpecification Comparison
| Parameter | EPM7512BQC208-7 | EPM7512BQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000B | MAX 7000B |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/O Pins | 176 | — |
| Maximum Internal Frequency | 90.1 MHz | — |
| Propagation Delay (tPD) | 7 ns | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V (2.5 V nominal) | — |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | In-System Programmable (EEPROM) |
| Package | 208-pin PQFP (28x28 mm) | — |
| Package Code | FQFP | — |
| Terminal Form | Gull Wing | — |
| Operating Temperature | 0C to 90C (commercial) | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| ECCN | 3A991 | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Configuration Retention | Non-volatile (no external configuration device required) | — |
| Series | — | MAX 7000B |
| Logic Elements / Blocks | — | 32 LABs (16 macrocells per LAB) |
| User I/Os | — | 176 |
| Propagation Delay (tpd) | — | 10 ns (max, pin-to-pin) |
| Internal Supply Voltage | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Package / Case | — | 208-pin PQFP (28x28 mm), S-PQFP-G208 |
| Architecture | — | CMOS, Multiple Array Matrix (MAX) second-generation |
| JTAG / Boundary Scan | — | IEEE Std 1149.1 compliant |
| MSL Level | — | [DATA_NEEDED: MSL Level] |