EPM9320ABC356-10 vs EPM9320BC356-15 Comparison
Detailed side-by-side comparison of EPM9320ABC356-10 by Altera and EPM9320BC356-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320ABC356-10 - MAX 9000 CPLD 6K Gates 320 Macros 356-BGA | Altera
EPM9320ABC356-10 Obsolete
Specification Comparison
| Parameter | EPM9320ABC356-10 | EPM9320BC356-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), third-generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | — |
| Maximum Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Delay (Speed Grade) | 10 ns | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (5.0 V typical) |
| In-System Programmability (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| Package | 356-pin BGA | 356-ball LBGA (BGA-356, 35x35 mm) |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Non-Volatile Configuration | Yes (EEPROM) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| Macrocells | — | 320 |
| Pin-to-Pin Delay (max) | — | 15 ns |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Programmable Type | — | In System Programmable |
| Operating Temperature Grade | — | Commercial |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |