EPM9320BC356-15 - MAX 9000 CPLD, 320 Macro, 15ns, BGA-356 | Altera
MPN: EPM9320BC356-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $52.63 | $52.63 |
| 10 | $47.5 | $475.00 |
| 100 | $42 | $4,200.00 |
| 500 | $36.5 | $18,250.00 |
| 1,000 | $31.2 | $31,200.00 |
Drop-in alternatives for EPM9320BC356-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320ABC356-10
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View Datasheet →EPM9320ALI84-10N
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View Datasheet →EPM9320ARI208-10
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View Datasheet →EPM9320BC356-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Macrocells | 320 |
| Pin-to-Pin Delay (max) | 15 ns |
| Process Technology | CMOS EEPROM |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V typical) |
| In-System Programmability | Yes (5.0-V ISP via JTAG) |
| JTAG Interface | IEEE Std. 1149.1 compliant |
| Package | 356-ball LBGA (BGA-356, 35x35 mm) |
| Mounting Type | Surface Mount |
| Programmable Type | In System Programmable |
| Operating Temperature Grade | Commercial |
EPM9320BC356-15 356-ball lbga (bga-356, 35x35 mm) Pin Configuration Guide
Complete pinout information for EPM9320BC356-15 (356-ball lbga (bga-356, 35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9320BC356-15.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320BC356-15 is suitable for 6 applications: High-Speed Glue Logic, Bus Interface and Protocol Bridging, Address Decoding and Chip-Select Generation, Industrial Control and Automation, Telecommunications Backplane Logic, Legacy Computing System Support.
High-Speed Glue Logic
The EPM9320BC356-15's 15 ns deterministic pin-to-pin delay and 320 macrocells make it well suited for high-speed glue logic between microprocessors, DSPs, ASICs, and memory subsystems. The MAX architecture delivers predictable timing that static timing analysis handles cleanly, avoiding the iterative place-and-route closure cycles required by FPGAs. With 5.0-V I/O tolerance, the part drops directly into legacy TTL-level buses. For new designs the -10 speed grade (EPM9320ABC356-10) is preferred where the budget allows; the -15 grade remains the workhorse for cost-sensitive glue-logic replacement.
Recommended
Bus Interface and Protocol Bridging
The EPM9320BC356-15 excels at bus interface and protocol bridging tasks, where its 320 macrocells provide ample headroom for state machines, FIFOs, and byte-order conversion logic. The JTAG-ISP support (IEEE 1149.1) allows field reconfiguration of bridge logic without board removal, which is invaluable for deployed telecom and industrial equipment. The 5.0-V tolerance simplifies interfacing with legacy PCI, ISA, and proprietary backplanes. Engineers designing multi-standard bridges should plan I/O bank utilization carefully given the BGA-356 footprint's high pin density.
Recommended
Address Decoding and Chip-Select Generation
Address decoding and chip-select generation are classic MAX 9000 applications where the EPM9320BC356-15's 320 macrocells and fast 15 ns propagation delay handle deep decode trees without timing penalties. The EEPROM-based configuration boots instantly at power-up, eliminating the configuration time of SRAM FPGAs - critical in systems that must respond to a host CPU's boot sequence within microseconds. With 5.0-V I/O, the part can drive legacy peripheral chips directly. Engineers building large decode trees should review the Quartus II fitter reports for macrocell utilization efficiency.
Recommended
Industrial Control and Automation
Industrial control and automation systems rely on the EPM9320BC356-15 for deterministic state-machine control of motor drives, PLCs, and sensor interfaces. The MAX architecture's predictable timing simplifies IEC 61131-3 functional safety certification, while the commercial temperature grade suits factory-floor enclosures. EEPROM-based configuration survives brown-outs and power cycles without external boot memory. For new industrial designs, confirm the part's lifecycle status (NRND) before committing and verify the JTAG-ISP chain remains compatible with the production test fixtures.
Recommended
Telecommunications Backplane Logic
Telecommunications backplanes depend on the EPM9320BC356-15 for fast, deterministic backplane glue logic, clock distribution steering, and TDM bus multiplexing. The 15 ns pin-to-pin delay accommodates legacy T1/E1 framer interfacing and proprietary backplane protocols up to several tens of MHz. Combined with 5.0-V tolerance and JTAG-ISP, the part remains in service across many carrier-grade systems still deployed in 2026. The BGA-356 package provides robust thermal performance and mechanical reliability required for telecom central-office environments.
Recommended
Legacy Computing System Support
The EPM9320BC356-15 is a critical support part for legacy computing systems that depend on a 5.0-V CPLD with 320 macrocells and BGA-356 footprint. These include industrial PCs, military/aerospace retrofits, and medical equipment with long service lives where the original component must be replaced with a pin-compatible part. The mature MAX 9000 family has a robust secondary-market supply chain through distributors like fpgax.net and altera-micro.com. Engineers maintaining these systems should plan lifecycle risk mitigation and consider pin-compatible MAX II upgrades where PCB rework is feasible.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320BC356-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ABC356-10 | EPM9320ALI84-10N | EPM9320ALC84-15 | EPM9320ARI208-10 | EPM9320ARC208-10 | EPM7512BTC144-7 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | BGA-356 | BGA-356 (same) | BGA-356 (logic-equivalent footprint) | BGA-356 (logic-equivalent footprint) | BGA-356 (logic-equivalent footprint) | BGA-356 (logic-equivalent footprint) | BGA-356 (same family footprint) |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 7000 |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 | 512 |
| Pin-to-Pin Delay (ns) | 15 | 10 | 10 | 15 | 10 | 10 | 7 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) | Yes (JTAG 1149.1) |
| Approx. Unit Price (USD) | $52.63 | Higher (faster grade) | Similar | Similar | Similar | Similar | [DATA_NEEDED] |
Key Differentiators
- Faster 10 ns speed grade in the same die and BGA-356 footprint (vs EPM9320ABC356-10)
- Smaller BGA-84 package option with the same silicon (vs EPM9320ALI84-10N)
- Higher macrocell density in the same MAX family (vs EPM7512BTC144-7)
Design Notes
The EPM9320BC356-15 requires a single 5.0-V VCC supply within 4.75 V to 5.25 V. Place a 0.1 uF decoupling capacitor close to every VCC ball, plus a single 10 uF bulk tantalum or ceramic capacitor near the package. The MAX 9000 family draws higher in-rush current during ISP programming - budget the regulator for at least 500 mA peak to avoid VCC droop during JTAG-ISP. Power sequencing is not required thanks to EEPROM-based configuration.
The BGA-356 (35x35 mm) package requires a 4- or 6-layer PCB with a continuous ground plane under the device for signal return paths and thermal dissipation. Use 0.5 mm ball pitch escape routing with microvia-in-pad or dog-bone fanout. BGA-356 reworking requires X-ray inspection or BGA rework station; plan assembly and prototype rework logistics accordingly. Maintain solid thermal vias under the center ball array to spread heat from the silicon die to inner copper planes.
Do not assume the EPM9320BC356-15 is 3.3-V tolerant - the MAX 9000 family is a 5.0-V-only part, and applying 3.3-V signals exceeding the VCC rail will forward-bias the I/O clamp diodes. When bridging to 3.3-V logic, use external level shifters such as the 74LVC245 or 74ACT245. Also verify the JTAG chain order in multi-device ISP configurations - the MAX 9000 must be placed correctly in the BSDL scan chain to avoid programming failures.
Compliance Information
Compliance data not present in verified web sources for this legacy Altera CPLD. RoHS and lead-free status should be verified with the manufacturer or distributor per the specific date code; MAX 9000 family pre-dates widespread RoHS transition.
